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From: Stafford Horne <shorne@gmail.com>
To: kernel test robot <lkp@intel.com>
Cc: Mateusz Holenko <mholenko@antmicro.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jiri Slaby <jslaby@suse.com>,
	devicetree@vger.kernel.org, linux-serial@vger.kernel.org,
	kbuild-all@lists.01.org, Karol Gugala <kgugala@antmicro.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>
Subject: Re: [PATCH v9 3/5] drivers/soc/litex: add LiteX SoC Controller driver
Date: Sun, 26 Jul 2020 06:14:16 +0900	[thread overview]
Message-ID: <20200725211416.GB80756@lianli.shorne-pla.net> (raw)
In-Reply-To: <202007251829.A4shNHeo%lkp@intel.com>

On Sat, Jul 25, 2020 at 06:29:51PM +0800, kernel test robot wrote:
> Hi Mateusz,
> 
> Thank you for the patch! Perhaps something to improve:
> 
> [auto build test WARNING on robh/for-next]
> [also build test WARNING on tty/tty-testing usb/usb-testing staging/staging-testing driver-core/driver-core-testing linus/master v5.8-rc6 next-20200724]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
> 
> url:    https://github.com/0day-ci/linux/commits/Mateusz-Holenko/LiteX-SoC-controller-and-LiteUART-serial-driver/20200722-183024
> base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
> config: openrisc-randconfig-s032-20200725 (attached as .config)
> compiler: or1k-linux-gcc (GCC) 9.3.0
> reproduce:
>         wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # apt-get install sparse
>         # sparse version: v0.6.2-93-g4c6cbe55-dirty
>         # save the attached .config to linux build tree
>         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=openrisc 

Note, this is OpenRISC

> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> 
> 
> sparse warnings: (new ones prefixed by >>)
> 
> >> drivers/soc/litex/litex_soc_ctrl.c:61:24: sparse: sparse: incorrect type in argument 1 (different base types) @@     expected unsigned int [usertype] value @@     got restricted __le32 [usertype] @@
> >> drivers/soc/litex/litex_soc_ctrl.c:61:24: sparse:     expected unsigned int [usertype] value
> >> drivers/soc/litex/litex_soc_ctrl.c:61:24: sparse:     got restricted __le32 [usertype]
> >> drivers/soc/litex/litex_soc_ctrl.c:77:32: sparse: sparse: cast to restricted __le32
> >> drivers/soc/litex/litex_soc_ctrl.c:77:32: sparse: sparse: cast to restricted __le32
> >> drivers/soc/litex/litex_soc_ctrl.c:77:32: sparse: sparse: cast to restricted __le32
> >> drivers/soc/litex/litex_soc_ctrl.c:77:32: sparse: sparse: cast to restricted __le32
> >> drivers/soc/litex/litex_soc_ctrl.c:77:32: sparse: sparse: cast to restricted __le32
> >> drivers/soc/litex/litex_soc_ctrl.c:77:32: sparse: sparse: cast to restricted __le32
>    drivers/soc/litex/litex_soc_ctrl.c: note: in included file (through arch/openrisc/include/asm/io.h, include/linux/io.h, include/linux/litex.h):

I think this is something I need to fix up in the openrisc io.h header.

It seems the sparse annotations are messed up.  Working on it...

-Stafford

>    include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
>    include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
>    include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
>    include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
>    include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
>    include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
>    include/asm-generic/io.h:225:22: sparse: sparse: incorrect type in argument 1 (different base types) @@     expected unsigned int [usertype] value @@     got restricted __le32 [usertype] @@
>    include/asm-generic/io.h:225:22: sparse:     expected unsigned int [usertype] value
>    include/asm-generic/io.h:225:22: sparse:     got restricted __le32 [usertype]
>    include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
>    include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
>    include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
>    include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
>    include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
>    include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
> 
> vim +61 drivers/soc/litex/litex_soc_ctrl.c
> 
>     32	
>     33	/*
>     34	 * LiteX SoC Generator, depending on the configuration,
>     35	 * can split a single logical CSR (Control & Status Register)
>     36	 * into a series of consecutive physical registers.
>     37	 *
>     38	 * For example, in the configuration with 8-bit CSR Bus,
>     39	 * 32-bit aligned (the default one for 32-bit CPUs) a 32-bit
>     40	 * logical CSR will be generated as four 32-bit physical registers,
>     41	 * each one containing one byte of meaningful data.
>     42	 *
>     43	 * For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus
>     44	 *
>     45	 * The purpose of `litex_set_reg`/`litex_get_reg` is to implement
>     46	 * the logic of writing to/reading from the LiteX CSR in a single
>     47	 * place that can be then reused by all LiteX drivers.
>     48	 */
>     49	void litex_set_reg(void __iomem *reg, unsigned long reg_size,
>     50			    unsigned long val)
>     51	{
>     52		unsigned long shifted_data, shift, i;
>     53		unsigned long flags;
>     54	
>     55		spin_lock_irqsave(&csr_lock, flags);
>     56	
>     57		for (i = 0; i < reg_size; ++i) {
>     58			shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT);
>     59			shifted_data = val >> shift;
>     60	
>   > 61			writel(cpu_to_le32(shifted_data), reg + (LITEX_REG_SIZE * i));
>     62		}
>     63	
>     64		spin_unlock_irqrestore(&csr_lock, flags);
>     65	}
>     66	EXPORT_SYMBOL_GPL(litex_set_reg);
>     67	
>     68	unsigned long litex_get_reg(void __iomem *reg, unsigned long reg_size)
>     69	{
>     70		unsigned long shifted_data, shift, i;
>     71		unsigned long result = 0;
>     72		unsigned long flags;
>     73	
>     74		spin_lock_irqsave(&csr_lock, flags);
>     75	
>     76		for (i = 0; i < reg_size; ++i) {
>   > 77			shifted_data = le32_to_cpu(readl(reg + (LITEX_REG_SIZE * i)));
>     78	
>     79			shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT);
>     80			result |= (shifted_data << shift);
>     81		}
>     82	
>     83		spin_unlock_irqrestore(&csr_lock, flags);
>     84	
>     85		return result;
>     86	}
>     87	EXPORT_SYMBOL_GPL(litex_get_reg);
>     88	
> 
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org



  reply	other threads:[~2020-07-25 21:14 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-22 10:27 [PATCH v9 0/5] LiteX SoC controller and LiteUART serial driver Mateusz Holenko
2020-07-22 10:27 ` [PATCH v9 1/5] dt-bindings: vendor: add vendor prefix for LiteX Mateusz Holenko
2020-07-22 10:27 ` [PATCH v9 2/5] dt-bindings: soc: document LiteX SoC Controller bindings Mateusz Holenko
2020-07-22 10:28 ` [PATCH v9 3/5] drivers/soc/litex: add LiteX SoC Controller driver Mateusz Holenko
2020-07-25 10:29   ` kernel test robot
2020-07-25 21:14     ` Stafford Horne [this message]
2020-07-26 23:36       ` Stafford Horne
2020-07-26 18:36   ` kernel test robot
2020-07-28  5:48   ` kernel test robot
2020-08-03  5:26   ` kernel test robot
2020-07-22 10:28 ` [PATCH v9 4/5] dt-bindings: serial: document LiteUART bindings Mateusz Holenko
2020-07-22 10:28 ` [PATCH v9 5/5] drivers/tty/serial: add LiteUART driver Mateusz Holenko

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