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[209.85.217.50]) by smtp.gmail.com with ESMTPSA id j197sm2531342vkc.19.2020.06.22.22.07.00 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Jun 2020 22:07:00 -0700 (PDT) Received: by mail-vs1-f50.google.com with SMTP id m25so10986576vsp.8 for ; Mon, 22 Jun 2020 22:07:00 -0700 (PDT) X-Received: by 2002:a67:e445:: with SMTP id n5mr18647007vsm.73.1592888819511; Mon, 22 Jun 2020 22:06:59 -0700 (PDT) MIME-Version: 1.0 References: <1591682194-32388-1-git-send-email-akashast@codeaurora.org> <1591682194-32388-5-git-send-email-akashast@codeaurora.org> In-Reply-To: <1591682194-32388-5-git-send-email-akashast@codeaurora.org> From: Doug Anderson Date: Mon, 22 Jun 2020 22:06:48 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH V7 RESEND 4/7] spi: spi-geni-qcom: Add interconnect support To: Akash Asthana Cc: Greg Kroah-Hartman , Andy Gross , Bjorn Andersson , Wolfram Sang , Mark Brown , Mark Rutland , Rob Herring , linux-i2c@vger.kernel.org, linux-spi , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Stephen Boyd , Manu Gautam , linux-arm-msm , linux-serial@vger.kernel.org, Matthias Kaehlcke , Evan Green , msavaliy@codeaurora.org, Rajendra Nayak Content-Type: text/plain; charset="UTF-8" Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Hi, On Mon, Jun 8, 2020 at 10:57 PM Akash Asthana wrote: > > Get the interconnect paths for SPI based Serial Engine device > and vote according to the current bus speed of the driver. > > Signed-off-by: Akash Asthana > Reviewed-by: Matthias Kaehlcke > --- > Changes in V2: > - As per Bjorn's comment, removed se == NULL check from geni_spi_icc_get > - As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure > - As per Bjorn's comment, introduced and using devm_of_icc_get API for getting > path handle > - As per Matthias comment, added error handling for icc_set_bw call > > Changes in V3: > - As per Matthias's comment, use helper ICC function from geni-se driver. > > Changes in V4: > - Move peak_bw guess as twice of avg_bw if nothing mentioned explicitly > to ICC core. > > Changes in V5: > - Use icc_enable/disable in power on/off call. > - Save some non-zero avg/peak value to ICC core by calling geni_icc_set_bw > from probe so that when resume/icc_enable is called NOC are running at > some non-zero value. No need to call icc_disable after BW vote because > device will resume and suspend before probe return and will leave ICC in > disabled state. > > Changes in V6: > - No change > > Changes in V7: > - As per Matthias's comment removed usage of peak_bw variable because we don't > have explicit peak requirement, we were voting peak = avg and this can be > tracked using single variable for avg bw. > > drivers/spi/spi-geni-qcom.c | 29 ++++++++++++++++++++++++++++- > 1 file changed, 28 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c > index c397242..2ace5c5 100644 > --- a/drivers/spi/spi-geni-qcom.c > +++ b/drivers/spi/spi-geni-qcom.c > @@ -234,6 +234,12 @@ static int setup_fifo_params(struct spi_device *spi_slv, > return ret; > } > > + /* Set BW quota for CPU as driver supports FIFO mode only. */ > + se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); > + ret = geni_icc_set_bw(se); > + if (ret) > + return ret; > + I haven't done a deep review of your patch, but a quick drive-by review since I happened to notice it while looking at this driver. You should probably also update the other path that's adjusting the "mas->cur_speed_hz" variable. Specifically see setup_fifo_xfer(). For bonus points, you could even unify the two paths. Perhaps you could pick and include it in your series (remove the WIP if you do). -Doug