* [PATCH v2 00/10] Add initial support for R8A7742/RZG1H SoC and iW-RainboW-G21D-Qseven development board support
@ 2020-05-03 21:46 Lad Prabhakar
2020-05-03 21:46 ` [PATCH v2 01/10] dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support Lad Prabhakar
` (9 more replies)
0 siblings, 10 replies; 32+ messages in thread
From: Lad Prabhakar @ 2020-05-03 21:46 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Vinod Koul,
Ulf Hansson, Linus Walleij, Greg Kroah-Hartman
Cc: linux-renesas-soc, devicetree, linux-kernel, dmaengine,
linux-mmc, linux-gpio, linux-serial, Prabhakar, Lad Prabhakar
Hi All,
This patch set adds initial support for R8A7742 SoC and
iW-RainboW-G21D-Qseven development board.
Cheers,
--Prabhakar
Changes for v2:
* Dropped patches 1-5 from v1[1] as they have been already queued.
* Split up the pfc for r8a7790 as common and automotive.
* Enabled dmac and scifa2 as part of initial SoC dtsi so that by default
board can be booted from eMMC.
* New patches 4, 7-10
* Dropped patches 12, 14-18 from v1[1] and will be posted after acceptance
of this series.
[1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=279727
Lad Prabhakar (10):
dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support
pinctrl: sh-pfc: r8a7790: Add r8a7742 PFC support
dt-bindings: serial: renesas,scifa: Document r8a7742 bindings
dt-bindings: mmc: renesas,mmcif: Document r8a7742 DT bindings
dt-bindings: renesas,rcar-dmac: Document r8a7742 support
ARM: dts: r8a7742: Initial SoC device tree
dt-bindings: arm: Document iW-RainboW-G21M-Qseven-RZG1H system on
module
dt-bindings: arm: Document iW-RainboW-G21D-Qseven-RZG1H board
ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM
ARM: dts: r8a7742-iwg21d-q7: Add support for iWave G21D-Q7 board based
on RZ/G1H
.../devicetree/bindings/arm/renesas.yaml | 10 +
.../bindings/dma/renesas,rcar-dmac.yaml | 1 +
.../devicetree/bindings/mmc/renesas,mmcif.txt | 1 +
.../bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 +
.../bindings/serial/renesas,scifa.yaml | 1 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 37 +
arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 53 ++
arch/arm/boot/dts/r8a7742.dtsi | 389 +++++++++
drivers/pinctrl/sh-pfc/Kconfig | 4 +
drivers/pinctrl/sh-pfc/Makefile | 1 +
drivers/pinctrl/sh-pfc/core.c | 6 +
drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 744 +++++++++---------
drivers/pinctrl/sh-pfc/sh_pfc.h | 1 +
14 files changed, 898 insertions(+), 352 deletions(-)
create mode 100644 arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
create mode 100644 arch/arm/boot/dts/r8a7742-iwg21m.dtsi
create mode 100644 arch/arm/boot/dts/r8a7742.dtsi
--
2.17.1
^ permalink raw reply [flat|nested] 32+ messages in thread* [PATCH v2 01/10] dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support 2020-05-03 21:46 [PATCH v2 00/10] Add initial support for R8A7742/RZG1H SoC and iW-RainboW-G21D-Qseven development board support Lad Prabhakar @ 2020-05-03 21:46 ` Lad Prabhakar 2020-05-12 22:17 ` Rob Herring 2020-05-03 21:46 ` [PATCH v2 02/10] pinctrl: sh-pfc: r8a7790: Add " Lad Prabhakar ` (8 subsequent siblings) 9 siblings, 1 reply; 32+ messages in thread From: Lad Prabhakar @ 2020-05-03 21:46 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman Cc: linux-renesas-soc, devicetree, linux-kernel, dmaengine, linux-mmc, linux-gpio, linux-serial, Prabhakar, Lad Prabhakar Document PFC support for the RZ/G1H (R8A7742) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- .../devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index 6eada23eaa31..b68613188c19 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -13,6 +13,7 @@ Required Properties: - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller. - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. + - "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller. - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller. - "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller. - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller. -- 2.17.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2 01/10] dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support 2020-05-03 21:46 ` [PATCH v2 01/10] dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support Lad Prabhakar @ 2020-05-12 22:17 ` Rob Herring 0 siblings, 0 replies; 32+ messages in thread From: Rob Herring @ 2020-05-12 22:17 UTC (permalink / raw) To: Lad Prabhakar Cc: Ulf Hansson, Rob Herring, linux-serial, dmaengine, Greg Kroah-Hartman, Prabhakar, Linus Walleij, linux-mmc, linux-gpio, Magnus Damm, Vinod Koul, Geert Uytterhoeven, linux-renesas-soc, linux-kernel, devicetree On Sun, 3 May 2020 22:46:45 +0100, Lad Prabhakar wrote: > Document PFC support for the RZ/G1H (R8A7742) SoC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > .../devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 02/10] pinctrl: sh-pfc: r8a7790: Add r8a7742 PFC support 2020-05-03 21:46 [PATCH v2 00/10] Add initial support for R8A7742/RZG1H SoC and iW-RainboW-G21D-Qseven development board support Lad Prabhakar 2020-05-03 21:46 ` [PATCH v2 01/10] dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support Lad Prabhakar @ 2020-05-03 21:46 ` Lad Prabhakar 2020-05-04 10:20 ` Geert Uytterhoeven 2020-05-03 21:46 ` [PATCH v2 03/10] dt-bindings: serial: renesas,scifa: Document r8a7742 bindings Lad Prabhakar ` (7 subsequent siblings) 9 siblings, 1 reply; 32+ messages in thread From: Lad Prabhakar @ 2020-05-03 21:46 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman Cc: linux-renesas-soc, devicetree, linux-kernel, dmaengine, linux-mmc, linux-gpio, linux-serial, Prabhakar, Lad Prabhakar Renesas RZ/G1H (R8A7742) is pin compatible with R-Car H2 (R8A7790), however it doesn't have several automotive specific peripherals. Add a r8a7790 specific pin groups/functions along with common pin groups/functions for supporting both r8a7790 and r8a7742 SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> --- drivers/pinctrl/sh-pfc/Kconfig | 4 + drivers/pinctrl/sh-pfc/Makefile | 1 + drivers/pinctrl/sh-pfc/core.c | 6 + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 744 ++++++++++++++------------- drivers/pinctrl/sh-pfc/sh_pfc.h | 1 + 5 files changed, 404 insertions(+), 352 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 9552851b96f1..c461a2f1927a 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -12,6 +12,7 @@ config PINCTRL_SH_PFC select PINCTRL_PFC_EMEV2 if ARCH_EMEV2 select PINCTRL_PFC_R8A73A4 if ARCH_R8A73A4 select PINCTRL_PFC_R8A7740 if ARCH_R8A7740 + select PINCTRL_PFC_R8A7742 if ARCH_R8A7742 select PINCTRL_PFC_R8A7743 if ARCH_R8A7743 select PINCTRL_PFC_R8A7744 if ARCH_R8A7744 select PINCTRL_PFC_R8A7745 if ARCH_R8A7745 @@ -74,6 +75,9 @@ config PINCTRL_PFC_R8A7740 bool "R-Mobile A1 pin control support" if COMPILE_TEST select PINCTRL_SH_PFC_GPIO +config PINCTRL_PFC_R8A7742 + bool "RZ/G1H pin control support" if COMPILE_TEST + config PINCTRL_PFC_R8A7743 bool "RZ/G1M pin control support" if COMPILE_TEST diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 9ebe321d24c4..3855d82069c9 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o +obj-$(CONFIG_PINCTRL_PFC_R8A7742) += pfc-r8a7790.o obj-$(CONFIG_PINCTRL_PFC_R8A7743) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7744) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index a2e19efa26e3..f368383cba61 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -485,6 +485,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7740_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7742 + { + .compatible = "renesas,pfc-r8a7742", + .data = &r8a7742_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7743 { .compatible = "renesas,pfc-r8a7743", diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 3366ed561cce..5b120549c6e9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -3938,297 +3938,304 @@ static const unsigned int vin3_clk_mux[] = { VI3_CLK_MARK, }; -static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(audio_clk_a), - SH_PFC_PIN_GROUP(audio_clk_b), - SH_PFC_PIN_GROUP(audio_clk_c), - SH_PFC_PIN_GROUP(audio_clkout), - SH_PFC_PIN_GROUP(audio_clkout_b), - SH_PFC_PIN_GROUP(audio_clkout_c), - SH_PFC_PIN_GROUP(audio_clkout_d), - SH_PFC_PIN_GROUP(avb_link), - SH_PFC_PIN_GROUP(avb_magic), - SH_PFC_PIN_GROUP(avb_phy_int), - SH_PFC_PIN_GROUP(avb_mdio), - SH_PFC_PIN_GROUP(avb_mii), - SH_PFC_PIN_GROUP(avb_gmii), - SH_PFC_PIN_GROUP(du_rgb666), - SH_PFC_PIN_GROUP(du_rgb888), - SH_PFC_PIN_GROUP(du_clk_out_0), - SH_PFC_PIN_GROUP(du_clk_out_1), - SH_PFC_PIN_GROUP(du_sync_0), - SH_PFC_PIN_GROUP(du_sync_1), - SH_PFC_PIN_GROUP(du_cde), - SH_PFC_PIN_GROUP(du0_clk_in), - SH_PFC_PIN_GROUP(du1_clk_in), - SH_PFC_PIN_GROUP(du2_clk_in), - SH_PFC_PIN_GROUP(eth_link), - SH_PFC_PIN_GROUP(eth_magic), - SH_PFC_PIN_GROUP(eth_mdio), - SH_PFC_PIN_GROUP(eth_rmii), - SH_PFC_PIN_GROUP(hscif0_data), - SH_PFC_PIN_GROUP(hscif0_clk), - SH_PFC_PIN_GROUP(hscif0_ctrl), - SH_PFC_PIN_GROUP(hscif0_data_b), - SH_PFC_PIN_GROUP(hscif0_ctrl_b), - SH_PFC_PIN_GROUP(hscif0_data_c), - SH_PFC_PIN_GROUP(hscif0_ctrl_c), - SH_PFC_PIN_GROUP(hscif0_data_d), - SH_PFC_PIN_GROUP(hscif0_ctrl_d), - SH_PFC_PIN_GROUP(hscif0_data_e), - SH_PFC_PIN_GROUP(hscif0_ctrl_e), - SH_PFC_PIN_GROUP(hscif0_data_f), - SH_PFC_PIN_GROUP(hscif0_ctrl_f), - SH_PFC_PIN_GROUP(hscif1_data), - SH_PFC_PIN_GROUP(hscif1_clk), - SH_PFC_PIN_GROUP(hscif1_ctrl), - SH_PFC_PIN_GROUP(hscif1_data_b), - SH_PFC_PIN_GROUP(hscif1_clk_b), - SH_PFC_PIN_GROUP(hscif1_ctrl_b), - SH_PFC_PIN_GROUP(i2c0), - SH_PFC_PIN_GROUP(i2c1), - SH_PFC_PIN_GROUP(i2c1_b), - SH_PFC_PIN_GROUP(i2c1_c), - SH_PFC_PIN_GROUP(i2c2), - SH_PFC_PIN_GROUP(i2c2_b), - SH_PFC_PIN_GROUP(i2c2_c), - SH_PFC_PIN_GROUP(i2c2_d), - SH_PFC_PIN_GROUP(i2c2_e), - SH_PFC_PIN_GROUP(i2c3), - SH_PFC_PIN_GROUP(iic0), - SH_PFC_PIN_GROUP(iic1), - SH_PFC_PIN_GROUP(iic1_b), - SH_PFC_PIN_GROUP(iic1_c), - SH_PFC_PIN_GROUP(iic2), - SH_PFC_PIN_GROUP(iic2_b), - SH_PFC_PIN_GROUP(iic2_c), - SH_PFC_PIN_GROUP(iic2_d), - SH_PFC_PIN_GROUP(iic2_e), - SH_PFC_PIN_GROUP(iic3), - SH_PFC_PIN_GROUP(intc_irq0), - SH_PFC_PIN_GROUP(intc_irq1), - SH_PFC_PIN_GROUP(intc_irq2), - SH_PFC_PIN_GROUP(intc_irq3), - SH_PFC_PIN_GROUP(mlb_3pin), - SH_PFC_PIN_GROUP(mmc0_data1), - SH_PFC_PIN_GROUP(mmc0_data4), - SH_PFC_PIN_GROUP(mmc0_data8), - SH_PFC_PIN_GROUP(mmc0_ctrl), - SH_PFC_PIN_GROUP(mmc1_data1), - SH_PFC_PIN_GROUP(mmc1_data4), - SH_PFC_PIN_GROUP(mmc1_data8), - SH_PFC_PIN_GROUP(mmc1_ctrl), - SH_PFC_PIN_GROUP(msiof0_clk), - SH_PFC_PIN_GROUP(msiof0_sync), - SH_PFC_PIN_GROUP(msiof0_ss1), - SH_PFC_PIN_GROUP(msiof0_ss2), - SH_PFC_PIN_GROUP(msiof0_rx), - SH_PFC_PIN_GROUP(msiof0_tx), - SH_PFC_PIN_GROUP(msiof0_clk_b), - SH_PFC_PIN_GROUP(msiof0_ss1_b), - SH_PFC_PIN_GROUP(msiof0_ss2_b), - SH_PFC_PIN_GROUP(msiof0_rx_b), - SH_PFC_PIN_GROUP(msiof0_tx_b), - SH_PFC_PIN_GROUP(msiof1_clk), - SH_PFC_PIN_GROUP(msiof1_sync), - SH_PFC_PIN_GROUP(msiof1_ss1), - SH_PFC_PIN_GROUP(msiof1_ss2), - SH_PFC_PIN_GROUP(msiof1_rx), - SH_PFC_PIN_GROUP(msiof1_tx), - SH_PFC_PIN_GROUP(msiof1_clk_b), - SH_PFC_PIN_GROUP(msiof1_ss1_b), - SH_PFC_PIN_GROUP(msiof1_ss2_b), - SH_PFC_PIN_GROUP(msiof1_rx_b), - SH_PFC_PIN_GROUP(msiof1_tx_b), - SH_PFC_PIN_GROUP(msiof2_clk), - SH_PFC_PIN_GROUP(msiof2_sync), - SH_PFC_PIN_GROUP(msiof2_ss1), - SH_PFC_PIN_GROUP(msiof2_ss2), - SH_PFC_PIN_GROUP(msiof2_rx), - SH_PFC_PIN_GROUP(msiof2_tx), - SH_PFC_PIN_GROUP(msiof3_clk), - SH_PFC_PIN_GROUP(msiof3_sync), - SH_PFC_PIN_GROUP(msiof3_ss1), - SH_PFC_PIN_GROUP(msiof3_ss2), - SH_PFC_PIN_GROUP(msiof3_rx), - SH_PFC_PIN_GROUP(msiof3_tx), - SH_PFC_PIN_GROUP(msiof3_clk_b), - SH_PFC_PIN_GROUP(msiof3_sync_b), - SH_PFC_PIN_GROUP(msiof3_rx_b), - SH_PFC_PIN_GROUP(msiof3_tx_b), - SH_PFC_PIN_GROUP(pwm0), - SH_PFC_PIN_GROUP(pwm0_b), - SH_PFC_PIN_GROUP(pwm1), - SH_PFC_PIN_GROUP(pwm1_b), - SH_PFC_PIN_GROUP(pwm2), - SH_PFC_PIN_GROUP(pwm3), - SH_PFC_PIN_GROUP(pwm4), - SH_PFC_PIN_GROUP(pwm5), - SH_PFC_PIN_GROUP(pwm6), - SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), - SH_PFC_PIN_GROUP(scif0_data), - SH_PFC_PIN_GROUP(scif0_clk), - SH_PFC_PIN_GROUP(scif0_ctrl), - SH_PFC_PIN_GROUP(scif0_data_b), - SH_PFC_PIN_GROUP(scif1_data), - SH_PFC_PIN_GROUP(scif1_clk), - SH_PFC_PIN_GROUP(scif1_ctrl), - SH_PFC_PIN_GROUP(scif1_data_b), - SH_PFC_PIN_GROUP(scif1_data_c), - SH_PFC_PIN_GROUP(scif1_data_d), - SH_PFC_PIN_GROUP(scif1_clk_d), - SH_PFC_PIN_GROUP(scif1_data_e), - SH_PFC_PIN_GROUP(scif1_clk_e), - SH_PFC_PIN_GROUP(scif2_data), - SH_PFC_PIN_GROUP(scif2_clk), - SH_PFC_PIN_GROUP(scif2_data_b), - SH_PFC_PIN_GROUP(scifa0_data), - SH_PFC_PIN_GROUP(scifa0_clk), - SH_PFC_PIN_GROUP(scifa0_ctrl), - SH_PFC_PIN_GROUP(scifa0_data_b), - SH_PFC_PIN_GROUP(scifa0_clk_b), - SH_PFC_PIN_GROUP(scifa0_ctrl_b), - SH_PFC_PIN_GROUP(scifa1_data), - SH_PFC_PIN_GROUP(scifa1_clk), - SH_PFC_PIN_GROUP(scifa1_ctrl), - SH_PFC_PIN_GROUP(scifa1_data_b), - SH_PFC_PIN_GROUP(scifa1_clk_b), - SH_PFC_PIN_GROUP(scifa1_ctrl_b), - SH_PFC_PIN_GROUP(scifa1_data_c), - SH_PFC_PIN_GROUP(scifa1_clk_c), - SH_PFC_PIN_GROUP(scifa1_ctrl_c), - SH_PFC_PIN_GROUP(scifa1_data_d), - SH_PFC_PIN_GROUP(scifa1_clk_d), - SH_PFC_PIN_GROUP(scifa1_ctrl_d), - SH_PFC_PIN_GROUP(scifa2_data), - SH_PFC_PIN_GROUP(scifa2_clk), - SH_PFC_PIN_GROUP(scifa2_ctrl), - SH_PFC_PIN_GROUP(scifa2_data_b), - SH_PFC_PIN_GROUP(scifa2_data_c), - SH_PFC_PIN_GROUP(scifa2_clk_c), - SH_PFC_PIN_GROUP(scifb0_data), - SH_PFC_PIN_GROUP(scifb0_clk), - SH_PFC_PIN_GROUP(scifb0_ctrl), - SH_PFC_PIN_GROUP(scifb0_data_b), - SH_PFC_PIN_GROUP(scifb0_clk_b), - SH_PFC_PIN_GROUP(scifb0_ctrl_b), - SH_PFC_PIN_GROUP(scifb0_data_c), - SH_PFC_PIN_GROUP(scifb1_data), - SH_PFC_PIN_GROUP(scifb1_clk), - SH_PFC_PIN_GROUP(scifb1_ctrl), - SH_PFC_PIN_GROUP(scifb1_data_b), - SH_PFC_PIN_GROUP(scifb1_clk_b), - SH_PFC_PIN_GROUP(scifb1_ctrl_b), - SH_PFC_PIN_GROUP(scifb1_data_c), - SH_PFC_PIN_GROUP(scifb1_data_d), - SH_PFC_PIN_GROUP(scifb1_data_e), - SH_PFC_PIN_GROUP(scifb1_clk_e), - SH_PFC_PIN_GROUP(scifb1_data_f), - SH_PFC_PIN_GROUP(scifb1_data_g), - SH_PFC_PIN_GROUP(scifb1_clk_g), - SH_PFC_PIN_GROUP(scifb2_data), - SH_PFC_PIN_GROUP(scifb2_clk), - SH_PFC_PIN_GROUP(scifb2_ctrl), - SH_PFC_PIN_GROUP(scifb2_data_b), - SH_PFC_PIN_GROUP(scifb2_clk_b), - SH_PFC_PIN_GROUP(scifb2_ctrl_b), - SH_PFC_PIN_GROUP(scifb2_data_c), - SH_PFC_PIN_GROUP(scif_clk), - SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), - SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_cd), - SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi1_cd), - SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_ctrl), - SH_PFC_PIN_GROUP(sdhi2_cd), - SH_PFC_PIN_GROUP(sdhi2_wp), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_ctrl), - SH_PFC_PIN_GROUP(sdhi3_cd), - SH_PFC_PIN_GROUP(sdhi3_wp), - SH_PFC_PIN_GROUP(ssi0_data), - SH_PFC_PIN_GROUP(ssi0129_ctrl), - SH_PFC_PIN_GROUP(ssi1_data), - SH_PFC_PIN_GROUP(ssi1_ctrl), - SH_PFC_PIN_GROUP(ssi2_data), - SH_PFC_PIN_GROUP(ssi2_ctrl), - SH_PFC_PIN_GROUP(ssi3_data), - SH_PFC_PIN_GROUP(ssi34_ctrl), - SH_PFC_PIN_GROUP(ssi4_data), - SH_PFC_PIN_GROUP(ssi4_ctrl), - SH_PFC_PIN_GROUP(ssi5), - SH_PFC_PIN_GROUP(ssi5_b), - SH_PFC_PIN_GROUP(ssi5_c), - SH_PFC_PIN_GROUP(ssi6), - SH_PFC_PIN_GROUP(ssi6_b), - SH_PFC_PIN_GROUP(ssi7_data), - SH_PFC_PIN_GROUP(ssi7_b_data), - SH_PFC_PIN_GROUP(ssi7_c_data), - SH_PFC_PIN_GROUP(ssi78_ctrl), - SH_PFC_PIN_GROUP(ssi78_b_ctrl), - SH_PFC_PIN_GROUP(ssi78_c_ctrl), - SH_PFC_PIN_GROUP(ssi8_data), - SH_PFC_PIN_GROUP(ssi8_b_data), - SH_PFC_PIN_GROUP(ssi8_c_data), - SH_PFC_PIN_GROUP(ssi9_data), - SH_PFC_PIN_GROUP(ssi9_ctrl), - SH_PFC_PIN_GROUP(tpu0_to0), - SH_PFC_PIN_GROUP(tpu0_to1), - SH_PFC_PIN_GROUP(tpu0_to2), - SH_PFC_PIN_GROUP(tpu0_to3), - SH_PFC_PIN_GROUP(usb0), - SH_PFC_PIN_GROUP(usb0_ovc_vbus), - SH_PFC_PIN_GROUP(usb1), - SH_PFC_PIN_GROUP(usb2), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), - SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), - VIN_DATA_PIN_GROUP(vin0_data, 4), - SH_PFC_PIN_GROUP(vin0_sync), - SH_PFC_PIN_GROUP(vin0_field), - SH_PFC_PIN_GROUP(vin0_clkenb), - SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 24), - VIN_DATA_PIN_GROUP(vin1_data, 20), - SH_PFC_PIN_GROUP(vin1_data18), - VIN_DATA_PIN_GROUP(vin1_data, 16), - VIN_DATA_PIN_GROUP(vin1_data, 12), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 4), - SH_PFC_PIN_GROUP(vin1_sync), - SH_PFC_PIN_GROUP(vin1_field), - SH_PFC_PIN_GROUP(vin1_clkenb), - SH_PFC_PIN_GROUP(vin1_clk), - VIN_DATA_PIN_GROUP(vin2_data, 24), - SH_PFC_PIN_GROUP(vin2_data18), - VIN_DATA_PIN_GROUP(vin2_data, 16), - VIN_DATA_PIN_GROUP(vin2_data, 8), - VIN_DATA_PIN_GROUP(vin2_data, 4), - SH_PFC_PIN_GROUP(vin2_sync), - SH_PFC_PIN_GROUP(vin2_field), - SH_PFC_PIN_GROUP(vin2_clkenb), - SH_PFC_PIN_GROUP(vin2_clk), - SH_PFC_PIN_GROUP(vin3_data8), - SH_PFC_PIN_GROUP(vin3_sync), - SH_PFC_PIN_GROUP(vin3_field), - SH_PFC_PIN_GROUP(vin3_clkenb), - SH_PFC_PIN_GROUP(vin3_clk), +static const struct { + struct sh_pfc_pin_group common[289]; + struct sh_pfc_pin_group automotive[1]; +} pinmux_groups = { + .common = { + SH_PFC_PIN_GROUP(audio_clk_a), + SH_PFC_PIN_GROUP(audio_clk_b), + SH_PFC_PIN_GROUP(audio_clk_c), + SH_PFC_PIN_GROUP(audio_clkout), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(audio_clkout_c), + SH_PFC_PIN_GROUP(audio_clkout_d), + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP(avb_mdio), + SH_PFC_PIN_GROUP(avb_mii), + SH_PFC_PIN_GROUP(avb_gmii), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out_0), + SH_PFC_PIN_GROUP(du_clk_out_1), + SH_PFC_PIN_GROUP(du_sync_0), + SH_PFC_PIN_GROUP(du_sync_1), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du0_clk_in), + SH_PFC_PIN_GROUP(du1_clk_in), + SH_PFC_PIN_GROUP(du2_clk_in), + SH_PFC_PIN_GROUP(eth_link), + SH_PFC_PIN_GROUP(eth_magic), + SH_PFC_PIN_GROUP(eth_mdio), + SH_PFC_PIN_GROUP(eth_rmii), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_ctrl_b), + SH_PFC_PIN_GROUP(hscif0_data_c), + SH_PFC_PIN_GROUP(hscif0_ctrl_c), + SH_PFC_PIN_GROUP(hscif0_data_d), + SH_PFC_PIN_GROUP(hscif0_ctrl_d), + SH_PFC_PIN_GROUP(hscif0_data_e), + SH_PFC_PIN_GROUP(hscif0_ctrl_e), + SH_PFC_PIN_GROUP(hscif0_data_f), + SH_PFC_PIN_GROUP(hscif0_ctrl_f), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c2_e), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(iic0), + SH_PFC_PIN_GROUP(iic1), + SH_PFC_PIN_GROUP(iic1_b), + SH_PFC_PIN_GROUP(iic1_c), + SH_PFC_PIN_GROUP(iic2), + SH_PFC_PIN_GROUP(iic2_b), + SH_PFC_PIN_GROUP(iic2_c), + SH_PFC_PIN_GROUP(iic2_d), + SH_PFC_PIN_GROUP(iic2_e), + SH_PFC_PIN_GROUP(iic3), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(mmc0_data1), + SH_PFC_PIN_GROUP(mmc0_data4), + SH_PFC_PIN_GROUP(mmc0_data8), + SH_PFC_PIN_GROUP(mmc0_ctrl), + SH_PFC_PIN_GROUP(mmc1_data1), + SH_PFC_PIN_GROUP(mmc1_data4), + SH_PFC_PIN_GROUP(mmc1_data8), + SH_PFC_PIN_GROUP(mmc1_ctrl), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_rx), + SH_PFC_PIN_GROUP(msiof0_tx), + SH_PFC_PIN_GROUP(msiof0_clk_b), + SH_PFC_PIN_GROUP(msiof0_ss1_b), + SH_PFC_PIN_GROUP(msiof0_ss2_b), + SH_PFC_PIN_GROUP(msiof0_rx_b), + SH_PFC_PIN_GROUP(msiof0_tx_b), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_rx), + SH_PFC_PIN_GROUP(msiof1_tx), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_rx_b), + SH_PFC_PIN_GROUP(msiof1_tx_b), + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_rx), + SH_PFC_PIN_GROUP(msiof2_tx), + SH_PFC_PIN_GROUP(msiof3_clk), + SH_PFC_PIN_GROUP(msiof3_sync), + SH_PFC_PIN_GROUP(msiof3_ss1), + SH_PFC_PIN_GROUP(msiof3_ss2), + SH_PFC_PIN_GROUP(msiof3_rx), + SH_PFC_PIN_GROUP(msiof3_tx), + SH_PFC_PIN_GROUP(msiof3_clk_b), + SH_PFC_PIN_GROUP(msiof3_sync_b), + SH_PFC_PIN_GROUP(msiof3_rx_b), + SH_PFC_PIN_GROUP(msiof3_tx_b), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2), + SH_PFC_PIN_GROUP(pwm3), + SH_PFC_PIN_GROUP(pwm4), + SH_PFC_PIN_GROUP(pwm5), + SH_PFC_PIN_GROUP(pwm6), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_data_d), + SH_PFC_PIN_GROUP(scif1_clk_d), + SH_PFC_PIN_GROUP(scif1_data_e), + SH_PFC_PIN_GROUP(scif1_clk_e), + SH_PFC_PIN_GROUP(scif2_data), + SH_PFC_PIN_GROUP(scif2_clk), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa0_data_b), + SH_PFC_PIN_GROUP(scifa0_clk_b), + SH_PFC_PIN_GROUP(scifa0_ctrl_b), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifa1_data_b), + SH_PFC_PIN_GROUP(scifa1_clk_b), + SH_PFC_PIN_GROUP(scifa1_ctrl_b), + SH_PFC_PIN_GROUP(scifa1_data_c), + SH_PFC_PIN_GROUP(scifa1_clk_c), + SH_PFC_PIN_GROUP(scifa1_ctrl_c), + SH_PFC_PIN_GROUP(scifa1_data_d), + SH_PFC_PIN_GROUP(scifa1_clk_d), + SH_PFC_PIN_GROUP(scifa1_ctrl_d), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk), + SH_PFC_PIN_GROUP(scifa2_ctrl), + SH_PFC_PIN_GROUP(scifa2_data_b), + SH_PFC_PIN_GROUP(scifa2_data_c), + SH_PFC_PIN_GROUP(scifa2_clk_c), + SH_PFC_PIN_GROUP(scifb0_data), + SH_PFC_PIN_GROUP(scifb0_clk), + SH_PFC_PIN_GROUP(scifb0_ctrl), + SH_PFC_PIN_GROUP(scifb0_data_b), + SH_PFC_PIN_GROUP(scifb0_clk_b), + SH_PFC_PIN_GROUP(scifb0_ctrl_b), + SH_PFC_PIN_GROUP(scifb0_data_c), + SH_PFC_PIN_GROUP(scifb1_data), + SH_PFC_PIN_GROUP(scifb1_clk), + SH_PFC_PIN_GROUP(scifb1_ctrl), + SH_PFC_PIN_GROUP(scifb1_data_b), + SH_PFC_PIN_GROUP(scifb1_clk_b), + SH_PFC_PIN_GROUP(scifb1_ctrl_b), + SH_PFC_PIN_GROUP(scifb1_data_c), + SH_PFC_PIN_GROUP(scifb1_data_d), + SH_PFC_PIN_GROUP(scifb1_data_e), + SH_PFC_PIN_GROUP(scifb1_clk_e), + SH_PFC_PIN_GROUP(scifb1_data_f), + SH_PFC_PIN_GROUP(scifb1_data_g), + SH_PFC_PIN_GROUP(scifb1_clk_g), + SH_PFC_PIN_GROUP(scifb2_data), + SH_PFC_PIN_GROUP(scifb2_clk), + SH_PFC_PIN_GROUP(scifb2_ctrl), + SH_PFC_PIN_GROUP(scifb2_data_b), + SH_PFC_PIN_GROUP(scifb2_clk_b), + SH_PFC_PIN_GROUP(scifb2_ctrl_b), + SH_PFC_PIN_GROUP(scifb2_data_c), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi0129_ctrl), + SH_PFC_PIN_GROUP(ssi1_data), + SH_PFC_PIN_GROUP(ssi1_ctrl), + SH_PFC_PIN_GROUP(ssi2_data), + SH_PFC_PIN_GROUP(ssi2_ctrl), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi34_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5), + SH_PFC_PIN_GROUP(ssi5_b), + SH_PFC_PIN_GROUP(ssi5_c), + SH_PFC_PIN_GROUP(ssi6), + SH_PFC_PIN_GROUP(ssi6_b), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi7_b_data), + SH_PFC_PIN_GROUP(ssi7_c_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi78_b_ctrl), + SH_PFC_PIN_GROUP(ssi78_c_ctrl), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi8_b_data), + SH_PFC_PIN_GROUP(ssi8_c_data), + SH_PFC_PIN_GROUP(ssi9_data), + SH_PFC_PIN_GROUP(ssi9_ctrl), + SH_PFC_PIN_GROUP(tpu0_to0), + SH_PFC_PIN_GROUP(tpu0_to1), + SH_PFC_PIN_GROUP(tpu0_to2), + SH_PFC_PIN_GROUP(tpu0_to3), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb0_ovc_vbus), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb2), + VIN_DATA_PIN_GROUP(vin0_data, 24), + VIN_DATA_PIN_GROUP(vin0_data, 20), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 16), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 8), + VIN_DATA_PIN_GROUP(vin0_data, 4), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), + SH_PFC_PIN_GROUP(vin0_clk), + VIN_DATA_PIN_GROUP(vin1_data, 24), + VIN_DATA_PIN_GROUP(vin1_data, 20), + SH_PFC_PIN_GROUP(vin1_data18), + VIN_DATA_PIN_GROUP(vin1_data, 16), + VIN_DATA_PIN_GROUP(vin1_data, 12), + VIN_DATA_PIN_GROUP(vin1_data, 10), + VIN_DATA_PIN_GROUP(vin1_data, 8), + VIN_DATA_PIN_GROUP(vin1_data, 4), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clk), + VIN_DATA_PIN_GROUP(vin2_data, 24), + SH_PFC_PIN_GROUP(vin2_data18), + VIN_DATA_PIN_GROUP(vin2_data, 16), + VIN_DATA_PIN_GROUP(vin2_data, 8), + VIN_DATA_PIN_GROUP(vin2_data, 4), + SH_PFC_PIN_GROUP(vin2_sync), + SH_PFC_PIN_GROUP(vin2_field), + SH_PFC_PIN_GROUP(vin2_clkenb), + SH_PFC_PIN_GROUP(vin2_clk), + SH_PFC_PIN_GROUP(vin3_data8), + SH_PFC_PIN_GROUP(vin3_sync), + SH_PFC_PIN_GROUP(vin3_field), + SH_PFC_PIN_GROUP(vin3_clkenb), + SH_PFC_PIN_GROUP(vin3_clk), + }, + .automotive = { + SH_PFC_PIN_GROUP(mlb_3pin), + } }; static const char * const audio_clk_groups[] = { @@ -4689,63 +4696,70 @@ static const char * const vin3_groups[] = { "vin3_clk", }; -static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(audio_clk), - SH_PFC_FUNCTION(avb), - SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(du0), - SH_PFC_FUNCTION(du1), - SH_PFC_FUNCTION(du2), - SH_PFC_FUNCTION(eth), - SH_PFC_FUNCTION(hscif0), - SH_PFC_FUNCTION(hscif1), - SH_PFC_FUNCTION(i2c0), - SH_PFC_FUNCTION(i2c1), - SH_PFC_FUNCTION(i2c2), - SH_PFC_FUNCTION(i2c3), - SH_PFC_FUNCTION(iic0), - SH_PFC_FUNCTION(iic1), - SH_PFC_FUNCTION(iic2), - SH_PFC_FUNCTION(iic3), - SH_PFC_FUNCTION(intc), - SH_PFC_FUNCTION(mlb), - SH_PFC_FUNCTION(mmc0), - SH_PFC_FUNCTION(mmc1), - SH_PFC_FUNCTION(msiof0), - SH_PFC_FUNCTION(msiof1), - SH_PFC_FUNCTION(msiof2), - SH_PFC_FUNCTION(msiof3), - SH_PFC_FUNCTION(pwm0), - SH_PFC_FUNCTION(pwm1), - SH_PFC_FUNCTION(pwm2), - SH_PFC_FUNCTION(pwm3), - SH_PFC_FUNCTION(pwm4), - SH_PFC_FUNCTION(pwm5), - SH_PFC_FUNCTION(pwm6), - SH_PFC_FUNCTION(qspi), - SH_PFC_FUNCTION(scif0), - SH_PFC_FUNCTION(scif1), - SH_PFC_FUNCTION(scif2), - SH_PFC_FUNCTION(scifa0), - SH_PFC_FUNCTION(scifa1), - SH_PFC_FUNCTION(scifa2), - SH_PFC_FUNCTION(scifb0), - SH_PFC_FUNCTION(scifb1), - SH_PFC_FUNCTION(scifb2), - SH_PFC_FUNCTION(scif_clk), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(sdhi3), - SH_PFC_FUNCTION(ssi), - SH_PFC_FUNCTION(tpu0), - SH_PFC_FUNCTION(usb0), - SH_PFC_FUNCTION(usb1), - SH_PFC_FUNCTION(usb2), - SH_PFC_FUNCTION(vin0), - SH_PFC_FUNCTION(vin1), - SH_PFC_FUNCTION(vin2), - SH_PFC_FUNCTION(vin3), +static const struct { + struct sh_pfc_function common[55]; + struct sh_pfc_function automotive[1]; +} pinmux_functions = { + .common = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(du1), + SH_PFC_FUNCTION(du2), + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(iic0), + SH_PFC_FUNCTION(iic1), + SH_PFC_FUNCTION(iic2), + SH_PFC_FUNCTION(iic3), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(mmc1), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(tpu0), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb2), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), + SH_PFC_FUNCTION(vin2), + SH_PFC_FUNCTION(vin3), + }, + .automotive = { + SH_PFC_FUNCTION(mlb), + } }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -5736,6 +5750,7 @@ static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { .pin_to_pocctrl = r8a7790_pin_to_pocctrl, }; +#ifdef CONFIG_PINCTRL_PFC_R8A7790 const struct sh_pfc_soc_info r8a7790_pinmux_info = { .name = "r8a77900_pfc", .ops = &r8a7790_pinmux_ops, @@ -5745,13 +5760,38 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = { .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common) + + ARRAY_SIZE(pinmux_groups.automotive), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common) + + ARRAY_SIZE(pinmux_functions.automotive), + + .cfg_regs = pinmux_config_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; +#endif + +#ifdef CONFIG_PINCTRL_PFC_R8A7742 +const struct sh_pfc_soc_info r8a7742_pinmux_info = { + .name = "r8a77420_pfc", + .ops = &r8a7790_pinmux_ops, + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common), .cfg_regs = pinmux_config_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; +#endif diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index d57e633e99c0..0f013827baf9 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -304,6 +304,7 @@ struct sh_pfc_soc_info { extern const struct sh_pfc_soc_info emev2_pinmux_info; extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; extern const struct sh_pfc_soc_info r8a7740_pinmux_info; +extern const struct sh_pfc_soc_info r8a7742_pinmux_info; extern const struct sh_pfc_soc_info r8a7743_pinmux_info; extern const struct sh_pfc_soc_info r8a7744_pinmux_info; extern const struct sh_pfc_soc_info r8a7745_pinmux_info; -- 2.17.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2 02/10] pinctrl: sh-pfc: r8a7790: Add r8a7742 PFC support 2020-05-03 21:46 ` [PATCH v2 02/10] pinctrl: sh-pfc: r8a7790: Add " Lad Prabhakar @ 2020-05-04 10:20 ` Geert Uytterhoeven 2020-05-04 13:41 ` Lad, Prabhakar 0 siblings, 1 reply; 32+ messages in thread From: Geert Uytterhoeven @ 2020-05-04 10:20 UTC (permalink / raw) To: Lad Prabhakar Cc: Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, dmaengine, Linux MMC List, open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, Prabhakar Hi Prabhakar, Thanks for the update! On Sun, May 3, 2020 at 11:47 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Renesas RZ/G1H (R8A7742) is pin compatible with R-Car H2 (R8A7790), > however it doesn't have several automotive specific peripherals. Add > a r8a7790 specific pin groups/functions along with common pin s/a r8a7790/automotive/? > groups/functions for supporting both r8a7790 and r8a7742 SoC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c > @@ -5736,6 +5750,7 @@ static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { > .pin_to_pocctrl = r8a7790_pin_to_pocctrl, > }; > > +#ifdef CONFIG_PINCTRL_PFC_R8A7790 > const struct sh_pfc_soc_info r8a7790_pinmux_info = { > .name = "r8a77900_pfc", > .ops = &r8a7790_pinmux_ops, > @@ -5745,13 +5760,38 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = { > > .pins = pinmux_pins, > .nr_pins = ARRAY_SIZE(pinmux_pins), > - .groups = pinmux_groups, > - .nr_groups = ARRAY_SIZE(pinmux_groups), > - .functions = pinmux_functions, > - .nr_functions = ARRAY_SIZE(pinmux_functions), > + .groups = pinmux_groups.common, > + .nr_groups = ARRAY_SIZE(pinmux_groups.common) + > + ARRAY_SIZE(pinmux_groups.automotive), > + .functions = pinmux_functions.common, > + .nr_functions = ARRAY_SIZE(pinmux_functions.common) + > + ARRAY_SIZE(pinmux_functions.automotive), > + > + .cfg_regs = pinmux_config_regs, > + > + .pinmux_data = pinmux_data, > + .pinmux_data_size = ARRAY_SIZE(pinmux_data), > +}; > +#endif > + > +#ifdef CONFIG_PINCTRL_PFC_R8A7742 > +const struct sh_pfc_soc_info r8a7742_pinmux_info = { > + .name = "r8a77420_pfc", > + .ops = &r8a7790_pinmux_ops, > + .unlock_reg = 0xe6060000, /* PMMR */ > + > + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, > + > + .pins = pinmux_pins, > + .nr_pins = ARRAY_SIZE(pinmux_pins), > + .groups = pinmux_groups.common, > + .nr_groups = ARRAY_SIZE(pinmux_groups.common), > + .functions = pinmux_functions.common, > + .nr_functions = ARRAY_SIZE(pinmux_functions.common), > > .cfg_regs = pinmux_config_regs, > > .pinmux_data = pinmux_data, > .pinmux_data_size = ARRAY_SIZE(pinmux_data), > }; > +#endif The r8a7742 section should be inserted before the r8a7790 section, to preserve sort order. No need to resend, will fix up while applying. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in sh-pfc-for-v5.8. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 02/10] pinctrl: sh-pfc: r8a7790: Add r8a7742 PFC support 2020-05-04 10:20 ` Geert Uytterhoeven @ 2020-05-04 13:41 ` Lad, Prabhakar 0 siblings, 0 replies; 32+ messages in thread From: Lad, Prabhakar @ 2020-05-04 13:41 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, dmaengine, Linux MMC List, open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS Hi Geert, Thank you for the review. On Mon, May 4, 2020 at 11:20 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > Thanks for the update! > > On Sun, May 3, 2020 at 11:47 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Renesas RZ/G1H (R8A7742) is pin compatible with R-Car H2 (R8A7790), > > however it doesn't have several automotive specific peripherals. Add > > a r8a7790 specific pin groups/functions along with common pin > > s/a r8a7790/automotive/? > > > groups/functions for supporting both r8a7790 and r8a7742 SoC. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > > --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c > > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c > > > @@ -5736,6 +5750,7 @@ static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { > > .pin_to_pocctrl = r8a7790_pin_to_pocctrl, > > }; > > > > +#ifdef CONFIG_PINCTRL_PFC_R8A7790 > > const struct sh_pfc_soc_info r8a7790_pinmux_info = { > > .name = "r8a77900_pfc", > > .ops = &r8a7790_pinmux_ops, > > @@ -5745,13 +5760,38 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = { > > > > .pins = pinmux_pins, > > .nr_pins = ARRAY_SIZE(pinmux_pins), > > - .groups = pinmux_groups, > > - .nr_groups = ARRAY_SIZE(pinmux_groups), > > - .functions = pinmux_functions, > > - .nr_functions = ARRAY_SIZE(pinmux_functions), > > + .groups = pinmux_groups.common, > > + .nr_groups = ARRAY_SIZE(pinmux_groups.common) + > > + ARRAY_SIZE(pinmux_groups.automotive), > > + .functions = pinmux_functions.common, > > + .nr_functions = ARRAY_SIZE(pinmux_functions.common) + > > + ARRAY_SIZE(pinmux_functions.automotive), > > + > > + .cfg_regs = pinmux_config_regs, > > + > > + .pinmux_data = pinmux_data, > > + .pinmux_data_size = ARRAY_SIZE(pinmux_data), > > +}; > > +#endif > > + > > +#ifdef CONFIG_PINCTRL_PFC_R8A7742 > > +const struct sh_pfc_soc_info r8a7742_pinmux_info = { > > + .name = "r8a77420_pfc", > > + .ops = &r8a7790_pinmux_ops, > > + .unlock_reg = 0xe6060000, /* PMMR */ > > + > > + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, > > + > > + .pins = pinmux_pins, > > + .nr_pins = ARRAY_SIZE(pinmux_pins), > > + .groups = pinmux_groups.common, > > + .nr_groups = ARRAY_SIZE(pinmux_groups.common), > > + .functions = pinmux_functions.common, > > + .nr_functions = ARRAY_SIZE(pinmux_functions.common), > > > > .cfg_regs = pinmux_config_regs, > > > > .pinmux_data = pinmux_data, > > .pinmux_data_size = ARRAY_SIZE(pinmux_data), > > }; > > +#endif > > The r8a7742 section should be inserted before the r8a7790 section, > to preserve sort order. > > No need to resend, will fix up while applying. > Thank you for taking care of it. Cheers, --Prabhakar > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > i.e. will queue in sh-pfc-for-v5.8. > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 03/10] dt-bindings: serial: renesas,scifa: Document r8a7742 bindings 2020-05-03 21:46 [PATCH v2 00/10] Add initial support for R8A7742/RZG1H SoC and iW-RainboW-G21D-Qseven development board support Lad Prabhakar 2020-05-03 21:46 ` [PATCH v2 01/10] dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support Lad Prabhakar 2020-05-03 21:46 ` [PATCH v2 02/10] pinctrl: sh-pfc: r8a7790: Add " Lad Prabhakar @ 2020-05-03 21:46 ` Lad Prabhakar 2020-05-12 22:20 ` Rob Herring 2020-05-03 21:46 ` [PATCH v2 04/10] dt-bindings: mmc: renesas,mmcif: Document r8a7742 DT bindings Lad Prabhakar ` (6 subsequent siblings) 9 siblings, 1 reply; 32+ messages in thread From: Lad Prabhakar @ 2020-05-03 21:46 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman Cc: linux-renesas-soc, devicetree, linux-kernel, dmaengine, linux-mmc, linux-gpio, linux-serial, Prabhakar, Lad Prabhakar RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible SCIFA ports, so document the SoC specific bindings. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- Documentation/devicetree/bindings/serial/renesas,scifa.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scifa.yaml b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml index b28bcb268854..97ddd76d700f 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scifa.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml @@ -24,6 +24,7 @@ properties: - items: - enum: + - renesas,scifa-r8a7742 # R8A7742 RZ/G1H - renesas,scifa-r8a7743 # R8A7743 RZ/G1M - renesas,scifa-r8a7744 # R8A7744 RZ/G1N - renesas,scifa-r8a7745 # R8A7745 RZ/G1E -- 2.17.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2 03/10] dt-bindings: serial: renesas,scifa: Document r8a7742 bindings 2020-05-03 21:46 ` [PATCH v2 03/10] dt-bindings: serial: renesas,scifa: Document r8a7742 bindings Lad Prabhakar @ 2020-05-12 22:20 ` Rob Herring 2020-05-28 19:36 ` Rob Herring 0 siblings, 1 reply; 32+ messages in thread From: Rob Herring @ 2020-05-12 22:20 UTC (permalink / raw) To: Lad Prabhakar Cc: Linus Walleij, linux-renesas-soc, linux-mmc, linux-serial, Greg Kroah-Hartman, Vinod Koul, Rob Herring, Prabhakar, devicetree, dmaengine, Magnus Damm, Geert Uytterhoeven, Ulf Hansson, linux-kernel, linux-gpio On Sun, 3 May 2020 22:46:47 +0100, Lad Prabhakar wrote: > RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible SCIFA ports, > so document the SoC specific bindings. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > Documentation/devicetree/bindings/serial/renesas,scifa.yaml | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 03/10] dt-bindings: serial: renesas,scifa: Document r8a7742 bindings 2020-05-12 22:20 ` Rob Herring @ 2020-05-28 19:36 ` Rob Herring 0 siblings, 0 replies; 32+ messages in thread From: Rob Herring @ 2020-05-28 19:36 UTC (permalink / raw) To: Lad Prabhakar Cc: Linus Walleij, linux-renesas-soc, linux-mmc, linux-serial, Greg Kroah-Hartman, Vinod Koul, Prabhakar, devicetree, dmaengine, Magnus Damm, Geert Uytterhoeven, Ulf Hansson, linux-kernel, linux-gpio On Tue, May 12, 2020 at 05:20:56PM -0500, Rob Herring wrote: > On Sun, 3 May 2020 22:46:47 +0100, Lad Prabhakar wrote: > > RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible SCIFA ports, > > so document the SoC specific bindings. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > --- > > Documentation/devicetree/bindings/serial/renesas,scifa.yaml | 1 + > > 1 file changed, 1 insertion(+) > > > > Acked-by: Rob Herring <robh@kernel.org> Geert asked me to apply this one, so I have now. Rob ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 04/10] dt-bindings: mmc: renesas,mmcif: Document r8a7742 DT bindings 2020-05-03 21:46 [PATCH v2 00/10] Add initial support for R8A7742/RZG1H SoC and iW-RainboW-G21D-Qseven development board support Lad Prabhakar ` (2 preceding siblings ...) 2020-05-03 21:46 ` [PATCH v2 03/10] dt-bindings: serial: renesas,scifa: Document r8a7742 bindings Lad Prabhakar @ 2020-05-03 21:46 ` Lad Prabhakar 2020-05-04 10:26 ` Geert Uytterhoeven 2020-05-03 21:46 ` [PATCH v2 05/10] dt-bindings: renesas,rcar-dmac: Document r8a7742 support Lad Prabhakar ` (5 subsequent siblings) 9 siblings, 1 reply; 32+ messages in thread From: Lad Prabhakar @ 2020-05-03 21:46 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman Cc: linux-renesas-soc, devicetree, linux-kernel, dmaengine, linux-mmc, linux-gpio, linux-serial, Prabhakar, Lad Prabhakar Add support for r8a7742 SoC. Renesas RZ/G1H (R8A7742) MMCIF is identical to the R-Car Gen2 family. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> --- Documentation/devicetree/bindings/mmc/renesas,mmcif.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt index c064af5838aa..42c703e246b9 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt +++ b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt @@ -11,6 +11,7 @@ Required properties: - "renesas,mmcif-r7s72100" for the MMCIF found in r7s72100 SoCs - "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs - "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs + - "renesas,mmcif-r8a7742" for the MMCIF found in r8a7742 SoCs - "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs - "renesas,mmcif-r8a7744" for the MMCIF found in r8a7744 SoCs - "renesas,mmcif-r8a7745" for the MMCIF found in r8a7745 SoCs -- 2.17.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2 04/10] dt-bindings: mmc: renesas,mmcif: Document r8a7742 DT bindings 2020-05-03 21:46 ` [PATCH v2 04/10] dt-bindings: mmc: renesas,mmcif: Document r8a7742 DT bindings Lad Prabhakar @ 2020-05-04 10:26 ` Geert Uytterhoeven 2020-05-04 13:43 ` Lad, Prabhakar 0 siblings, 1 reply; 32+ messages in thread From: Geert Uytterhoeven @ 2020-05-04 10:26 UTC (permalink / raw) To: Lad Prabhakar Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, dmaengine, Linux MMC List, open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, Prabhakar Hi Prabhakar, On Sun, May 3, 2020 at 11:47 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add support for r8a7742 SoC. Renesas RZ/G1H (R8A7742) MMCIF is identical > to the R-Car Gen2 family. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Thanks for your patch! > --- a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt > +++ b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt > @@ -11,6 +11,7 @@ Required properties: > - "renesas,mmcif-r7s72100" for the MMCIF found in r7s72100 SoCs > - "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs > - "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs > + - "renesas,mmcif-r8a7742" for the MMCIF found in r8a7742 SoCs > - "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs > - "renesas,mmcif-r8a7744" for the MMCIF found in r8a7744 SoCs > - "renesas,mmcif-r8a7745" for the MMCIF found in r8a7745 SoCs Please also update the paragraph stating the number of interrupts (1 for r8a7742). With that fixed: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 04/10] dt-bindings: mmc: renesas,mmcif: Document r8a7742 DT bindings 2020-05-04 10:26 ` Geert Uytterhoeven @ 2020-05-04 13:43 ` Lad, Prabhakar 0 siblings, 0 replies; 32+ messages in thread From: Lad, Prabhakar @ 2020-05-04 13:43 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, dmaengine, Linux MMC List, open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS Hi Geert, Thank you for the review. On Mon, May 4, 2020 at 11:26 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Sun, May 3, 2020 at 11:47 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Add support for r8a7742 SoC. Renesas RZ/G1H (R8A7742) MMCIF is identical > > to the R-Car Gen2 family. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > Thanks for your patch! > > > --- a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt > > +++ b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt > > @@ -11,6 +11,7 @@ Required properties: > > - "renesas,mmcif-r7s72100" for the MMCIF found in r7s72100 SoCs > > - "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs > > - "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs > > + - "renesas,mmcif-r8a7742" for the MMCIF found in r8a7742 SoCs > > - "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs > > - "renesas,mmcif-r8a7744" for the MMCIF found in r8a7744 SoCs > > - "renesas,mmcif-r8a7745" for the MMCIF found in r8a7745 SoCs > > Please also update the paragraph stating the number of interrupts > (1 for r8a7742). > Oops missed that, will fixup and post a v3. > With that fixed: > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Thanks for the Ack. Cheers, --Prabhakar > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 05/10] dt-bindings: renesas,rcar-dmac: Document r8a7742 support 2020-05-03 21:46 [PATCH v2 00/10] Add initial support for R8A7742/RZG1H SoC and iW-RainboW-G21D-Qseven development board support Lad Prabhakar ` (3 preceding siblings ...) 2020-05-03 21:46 ` [PATCH v2 04/10] dt-bindings: mmc: renesas,mmcif: Document r8a7742 DT bindings Lad Prabhakar @ 2020-05-03 21:46 ` Lad Prabhakar 2020-05-12 22:21 ` Rob Herring 2020-08-27 11:08 ` Lad, Prabhakar 2020-05-03 21:46 ` [PATCH v2 06/10] ARM: dts: r8a7742: Initial SoC device tree Lad Prabhakar ` (4 subsequent siblings) 9 siblings, 2 replies; 32+ messages in thread From: Lad Prabhakar @ 2020-05-03 21:46 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman Cc: linux-renesas-soc, devicetree, linux-kernel, dmaengine, linux-mmc, linux-gpio, linux-serial, Prabhakar, Lad Prabhakar Renesas RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers. Document RZ/G1H (also known as R8A7742) SoC bindings. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml index b842dfd96a89..ad471cf5675b 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml @@ -16,6 +16,7 @@ properties: compatible: items: - enum: + - renesas,dmac-r8a7742 # RZ/G1H - renesas,dmac-r8a7743 # RZ/G1M - renesas,dmac-r8a7744 # RZ/G1N - renesas,dmac-r8a7745 # RZ/G1E -- 2.17.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2 05/10] dt-bindings: renesas,rcar-dmac: Document r8a7742 support 2020-05-03 21:46 ` [PATCH v2 05/10] dt-bindings: renesas,rcar-dmac: Document r8a7742 support Lad Prabhakar @ 2020-05-12 22:21 ` Rob Herring 2020-08-27 11:08 ` Lad, Prabhakar 1 sibling, 0 replies; 32+ messages in thread From: Rob Herring @ 2020-05-12 22:21 UTC (permalink / raw) To: Lad Prabhakar Cc: Prabhakar, Geert Uytterhoeven, devicetree, linux-renesas-soc, Ulf Hansson, Rob Herring, linux-gpio, dmaengine, Greg Kroah-Hartman, linux-kernel, Linus Walleij, Vinod Koul, linux-serial, Magnus Damm, linux-mmc On Sun, 3 May 2020 22:46:49 +0100, Lad Prabhakar wrote: > Renesas RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers. > Document RZ/G1H (also known as R8A7742) SoC bindings. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 05/10] dt-bindings: renesas,rcar-dmac: Document r8a7742 support 2020-05-03 21:46 ` [PATCH v2 05/10] dt-bindings: renesas,rcar-dmac: Document r8a7742 support Lad Prabhakar 2020-05-12 22:21 ` Rob Herring @ 2020-08-27 11:08 ` Lad, Prabhakar 2020-09-03 7:12 ` Vinod Koul 1 sibling, 1 reply; 32+ messages in thread From: Lad, Prabhakar @ 2020-08-27 11:08 UTC (permalink / raw) To: Vinod Koul Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Lad Prabhakar, LKML, dmaengine, Linux MMC List, open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS Hi Vinod, On Sun, May 3, 2020 at 10:47 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Renesas RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers. > Document RZ/G1H (also known as R8A7742) SoC bindings. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml | 1 + > 1 file changed, 1 insertion(+) > This patch is not present in linux-next yet, could you please take care of it. Cheers, Prabhakar ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 05/10] dt-bindings: renesas,rcar-dmac: Document r8a7742 support 2020-08-27 11:08 ` Lad, Prabhakar @ 2020-09-03 7:12 ` Vinod Koul 0 siblings, 0 replies; 32+ messages in thread From: Vinod Koul @ 2020-09-03 7:12 UTC (permalink / raw) To: Lad, Prabhakar Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Lad Prabhakar, LKML, dmaengine, Linux MMC List, open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS On 27-08-20, 12:08, Lad, Prabhakar wrote: > Hi Vinod, > > On Sun, May 3, 2020 at 10:47 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > > Renesas RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers. > > Document RZ/G1H (also known as R8A7742) SoC bindings. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > --- > > Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml | 1 + > > 1 file changed, 1 insertion(+) > > > This patch is not present in linux-next yet, could you please take care of it. Can you please resend -- ~Vinod ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 06/10] ARM: dts: r8a7742: Initial SoC device tree 2020-05-03 21:46 [PATCH v2 00/10] Add initial support for R8A7742/RZG1H SoC and iW-RainboW-G21D-Qseven development board support Lad Prabhakar ` (4 preceding siblings ...) 2020-05-03 21:46 ` [PATCH v2 05/10] dt-bindings: renesas,rcar-dmac: Document r8a7742 support Lad Prabhakar @ 2020-05-03 21:46 ` Lad Prabhakar 2020-05-04 10:28 ` Geert Uytterhoeven 2020-05-03 21:46 ` [PATCH v2 07/10] dt-bindings: arm: Document iW-RainboW-G21M-Qseven-RZG1H system on module Lad Prabhakar ` (3 subsequent siblings) 9 siblings, 1 reply; 32+ messages in thread From: Lad Prabhakar @ 2020-05-03 21:46 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman Cc: linux-renesas-soc, devicetree, linux-kernel, dmaengine, linux-mmc, linux-gpio, linux-serial, Prabhakar, Lad Prabhakar The initial R8A7742 SoC device tree including CPU[0-8], PMU, PFC, CPG, RST, SYSC, ICRAM[0-2], SCIFA2, MMC1, DMAC[0-1], GIC, PRR, timer and the required clock descriptions. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> --- arch/arm/boot/dts/r8a7742.dtsi | 389 +++++++++++++++++++++++++++++++++ 1 file changed, 389 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7742.dtsi diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi new file mode 100644 index 000000000000..8d64cd0a2137 --- /dev/null +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a7742 SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include <dt-bindings/clock/r8a7742-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/power/r8a7742-sysc.h> + +/ { + compatible = "renesas,r8a7742"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU1>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU2>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU3>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU0>; + next-level-cache = <&L2_CA7>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU1>; + next-level-cache = <&L2_CA7>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU2>; + next-level-cache = <&L2_CA7>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU3>; + next-level-cache = <&L2_CA7>; + }; + + L2_CA15: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7742_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA7: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A7742_PD_CA7_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + pmu-0 { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + pmu-1 { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7742"; + reg = <0 0xe6060000 0 0x250>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7742-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7742-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7742-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63a0000 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe6300000 0x40000>; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + mmcif1: mmc@ee220000 { + compatible = "renesas,mmcif-r8a7742", + "renesas,sh-mmcif"; + reg = <0 0xee220000 0 0x80>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 305>; + dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, + <&dmac1 0xe1>, <&dmac1 0xe2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 305>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; -- 2.17.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2 06/10] ARM: dts: r8a7742: Initial SoC device tree 2020-05-03 21:46 ` [PATCH v2 06/10] ARM: dts: r8a7742: Initial SoC device tree Lad Prabhakar @ 2020-05-04 10:28 ` Geert Uytterhoeven 0 siblings, 0 replies; 32+ messages in thread From: Geert Uytterhoeven @ 2020-05-04 10:28 UTC (permalink / raw) To: Lad Prabhakar Cc: Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, dmaengine, Linux MMC List, open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, Prabhakar Hi Prabhakar, On Sun, May 3, 2020 at 11:47 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > The initial R8A7742 SoC device tree including CPU[0-8], PMU, PFC, > CPG, RST, SYSC, ICRAM[0-2], SCIFA2, MMC1, DMAC[0-1], GIC, PRR, timer > and the required clock descriptions. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > --- /dev/null > +++ b/arch/arm/boot/dts/r8a7742.dtsi > + icram2: sram@e6300000 { > + compatible = "mmio-sram"; > + reg = <0 0xe6300000 0 0x40000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0xe6300000 0x40000>; > + }; > + > + scifa2: serial@e6c60000 { > + compatible = "renesas,scifa-r8a7742", > + "renesas,rcar-gen2-scifa", "renesas,scifa"; > + reg = <0 0xe6c60000 0 0x40>; > + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 202>; > + clock-names = "fck"; > + dmas = <&dmac0 0x27>, <&dmac0 0x28>, > + <&dmac1 0x27>, <&dmac1 0x28>; > + dma-names = "tx", "rx", "tx", "rx"; > + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; > + resets = <&cpg 202>; > + status = "disabled"; > + }; > + > + mmcif1: mmc@ee220000 { > + compatible = "renesas,mmcif-r8a7742", > + "renesas,sh-mmcif"; > + reg = <0 0xee220000 0 0x80>; > + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 305>; > + dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, > + <&dmac1 0xe1>, <&dmac1 0xe2>; > + dma-names = "tx", "rx", "tx", "rx"; > + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; > + resets = <&cpg 305>; > + reg-io-width = <4>; > + status = "disabled"; > + max-frequency = <97500000>; > + }; > + > + dmac0: dma-controller@e6700000 { > + compatible = "renesas,dmac-r8a7742", > + "renesas,rcar-dmac"; > + reg = <0 0xe6700000 0 0x20000>; > + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "error", > + "ch0", "ch1", "ch2", "ch3", > + "ch4", "ch5", "ch6", "ch7", > + "ch8", "ch9", "ch10", "ch11", > + "ch12", "ch13", "ch14"; > + clocks = <&cpg CPG_MOD 219>; > + clock-names = "fck"; > + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; > + resets = <&cpg 219>; > + #dma-cells = <1>; > + dma-channels = <15>; > + }; > + > + dmac1: dma-controller@e6720000 { > + compatible = "renesas,dmac-r8a7742", > + "renesas,rcar-dmac"; > + reg = <0 0xe6720000 0 0x20000>; > + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "error", > + "ch0", "ch1", "ch2", "ch3", > + "ch4", "ch5", "ch6", "ch7", > + "ch8", "ch9", "ch10", "ch11", > + "ch12", "ch13", "ch14"; > + clocks = <&cpg CPG_MOD 218>; > + clock-names = "fck"; > + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; > + resets = <&cpg 218>; > + #dma-cells = <1>; > + dma-channels = <15>; > + }; To preserve sort order, the DMAC nodes should be moved up. No need to resend, will fix up while applying. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.8. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 07/10] dt-bindings: arm: Document iW-RainboW-G21M-Qseven-RZG1H system on module 2020-05-03 21:46 [PATCH v2 00/10] Add initial support for R8A7742/RZG1H SoC and iW-RainboW-G21D-Qseven development board support Lad Prabhakar ` (5 preceding siblings ...) 2020-05-03 21:46 ` [PATCH v2 06/10] ARM: dts: r8a7742: Initial SoC device tree Lad Prabhakar @ 2020-05-03 21:46 ` Lad Prabhakar 2020-05-04 11:21 ` Geert Uytterhoeven 2020-05-12 22:21 ` Rob Herring 2020-05-03 21:46 ` [PATCH v2 08/10] dt-bindings: arm: Document iW-RainboW-G21D-Qseven-RZG1H board Lad Prabhakar ` (2 subsequent siblings) 9 siblings, 2 replies; 32+ messages in thread From: Lad Prabhakar @ 2020-05-03 21:46 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman Cc: linux-renesas-soc, devicetree, linux-kernel, dmaengine, linux-mmc, linux-gpio, linux-serial, Prabhakar, Lad Prabhakar Document the iW-RainboW-G21M-Qseven-RZG1H device tree bindings, listing it as a supported system on module. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> --- Documentation/devicetree/bindings/arm/renesas.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 611094d9186b..8e85e1c72fc4 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -54,6 +54,9 @@ properties: - description: RZ/G1H (R8A77420) items: + - enum: + # iWave Systems RZ/G1H Qseven System On Module (iW-RainboW-G21M-Qseven) + - iwave,g21m - const: renesas,r8a7742 - description: RZ/G1M (R8A77430) -- 2.17.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2 07/10] dt-bindings: arm: Document iW-RainboW-G21M-Qseven-RZG1H system on module 2020-05-03 21:46 ` [PATCH v2 07/10] dt-bindings: arm: Document iW-RainboW-G21M-Qseven-RZG1H system on module Lad Prabhakar @ 2020-05-04 11:21 ` Geert Uytterhoeven 2020-05-12 22:21 ` Rob Herring 1 sibling, 0 replies; 32+ messages in thread From: Geert Uytterhoeven @ 2020-05-04 11:21 UTC (permalink / raw) To: Lad Prabhakar Cc: Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, dmaengine, Linux MMC List, open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, Prabhakar On Sun, May 3, 2020 at 11:47 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Document the iW-RainboW-G21M-Qseven-RZG1H device tree bindings, > listing it as a supported system on module. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.8. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 07/10] dt-bindings: arm: Document iW-RainboW-G21M-Qseven-RZG1H system on module 2020-05-03 21:46 ` [PATCH v2 07/10] dt-bindings: arm: Document iW-RainboW-G21M-Qseven-RZG1H system on module Lad Prabhakar 2020-05-04 11:21 ` Geert Uytterhoeven @ 2020-05-12 22:21 ` Rob Herring 1 sibling, 0 replies; 32+ messages in thread From: Rob Herring @ 2020-05-12 22:21 UTC (permalink / raw) To: Lad Prabhakar Cc: Rob Herring, dmaengine, linux-mmc, linux-serial, Linus Walleij, linux-gpio, Geert Uytterhoeven, Vinod Koul, linux-kernel, linux-renesas-soc, devicetree, Ulf Hansson, Greg Kroah-Hartman, Prabhakar, Magnus Damm On Sun, 3 May 2020 22:46:51 +0100, Lad Prabhakar wrote: > Document the iW-RainboW-G21M-Qseven-RZG1H device tree bindings, > listing it as a supported system on module. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > --- > Documentation/devicetree/bindings/arm/renesas.yaml | 3 +++ > 1 file changed, 3 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 08/10] dt-bindings: arm: Document iW-RainboW-G21D-Qseven-RZG1H board 2020-05-03 21:46 [PATCH v2 00/10] Add initial support for R8A7742/RZG1H SoC and iW-RainboW-G21D-Qseven development board support Lad Prabhakar ` (6 preceding siblings ...) 2020-05-03 21:46 ` [PATCH v2 07/10] dt-bindings: arm: Document iW-RainboW-G21M-Qseven-RZG1H system on module Lad Prabhakar @ 2020-05-03 21:46 ` Lad Prabhakar 2020-05-04 11:21 ` Geert Uytterhoeven 2020-05-12 22:21 ` Rob Herring 2020-05-03 21:46 ` [PATCH v2 09/10] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM Lad Prabhakar 2020-05-03 21:46 ` [PATCH v2 10/10] ARM: dts: r8a7742-iwg21d-q7: Add support for iWave G21D-Q7 board based on RZ/G1H Lad Prabhakar 9 siblings, 2 replies; 32+ messages in thread From: Lad Prabhakar @ 2020-05-03 21:46 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman Cc: linux-renesas-soc, devicetree, linux-kernel, dmaengine, linux-mmc, linux-gpio, linux-serial, Prabhakar, Lad Prabhakar Document the iW-RainboW-G21D-Qseven-RZG1H device tree bindings, listing it as a supported board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> --- Documentation/devicetree/bindings/arm/renesas.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 8e85e1c72fc4..b7d2e921150a 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -59,6 +59,13 @@ properties: - iwave,g21m - const: renesas,r8a7742 + - items: + - enum: + # iWave Systems RZ/G1H Qseven Development Platform (iW-RainboW-G21D-Qseven) + - iwave,g21d + - const: iwave,g21m + - const: renesas,r8a7742 + - description: RZ/G1M (R8A77430) items: - enum: -- 2.17.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2 08/10] dt-bindings: arm: Document iW-RainboW-G21D-Qseven-RZG1H board 2020-05-03 21:46 ` [PATCH v2 08/10] dt-bindings: arm: Document iW-RainboW-G21D-Qseven-RZG1H board Lad Prabhakar @ 2020-05-04 11:21 ` Geert Uytterhoeven 2020-05-12 22:21 ` Rob Herring 1 sibling, 0 replies; 32+ messages in thread From: Geert Uytterhoeven @ 2020-05-04 11:21 UTC (permalink / raw) To: Lad Prabhakar Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, dmaengine, Linux MMC List, open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, Prabhakar On Sun, May 3, 2020 at 11:47 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Document the iW-RainboW-G21D-Qseven-RZG1H device tree bindings, > listing it as a supported board. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.8. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 08/10] dt-bindings: arm: Document iW-RainboW-G21D-Qseven-RZG1H board 2020-05-03 21:46 ` [PATCH v2 08/10] dt-bindings: arm: Document iW-RainboW-G21D-Qseven-RZG1H board Lad Prabhakar 2020-05-04 11:21 ` Geert Uytterhoeven @ 2020-05-12 22:21 ` Rob Herring 1 sibling, 0 replies; 32+ messages in thread From: Rob Herring @ 2020-05-12 22:21 UTC (permalink / raw) To: Lad Prabhakar Cc: dmaengine, linux-kernel, linux-renesas-soc, Prabhakar, Magnus Damm, Linus Walleij, linux-mmc, Geert Uytterhoeven, Greg Kroah-Hartman, Ulf Hansson, linux-serial, Rob Herring, devicetree, Vinod Koul, linux-gpio On Sun, 3 May 2020 22:46:52 +0100, Lad Prabhakar wrote: > Document the iW-RainboW-G21D-Qseven-RZG1H device tree bindings, > listing it as a supported board. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > --- > Documentation/devicetree/bindings/arm/renesas.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 09/10] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM 2020-05-03 21:46 [PATCH v2 00/10] Add initial support for R8A7742/RZG1H SoC and iW-RainboW-G21D-Qseven development board support Lad Prabhakar ` (7 preceding siblings ...) 2020-05-03 21:46 ` [PATCH v2 08/10] dt-bindings: arm: Document iW-RainboW-G21D-Qseven-RZG1H board Lad Prabhakar @ 2020-05-03 21:46 ` Lad Prabhakar 2020-05-04 13:01 ` Geert Uytterhoeven 2020-05-03 21:46 ` [PATCH v2 10/10] ARM: dts: r8a7742-iwg21d-q7: Add support for iWave G21D-Q7 board based on RZ/G1H Lad Prabhakar 9 siblings, 1 reply; 32+ messages in thread From: Lad Prabhakar @ 2020-05-03 21:46 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman Cc: linux-renesas-soc, devicetree, linux-kernel, dmaengine, linux-mmc, linux-gpio, linux-serial, Prabhakar, Lad Prabhakar Add support for iWave RZ/G1H Qseven System On Module. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> --- arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 53 +++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7742-iwg21m.dtsi diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi new file mode 100644 index 000000000000..3d22de47f337 --- /dev/null +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave RZ/G1H Qseven SOM + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include "r8a7742.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "iwave,g21m", "renesas,r8a7742"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x20000000>; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + mmc1_pins: mmc1 { + groups = "mmc1_data4", "mmc1_ctrl"; + function = "mmc1"; + }; +}; + +&mmcif1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <4>; + non-removable; + status = "okay"; +}; -- 2.17.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2 09/10] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM 2020-05-03 21:46 ` [PATCH v2 09/10] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM Lad Prabhakar @ 2020-05-04 13:01 ` Geert Uytterhoeven 2020-05-04 14:20 ` Lad, Prabhakar 0 siblings, 1 reply; 32+ messages in thread From: Geert Uytterhoeven @ 2020-05-04 13:01 UTC (permalink / raw) To: Lad Prabhakar Cc: Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, dmaengine, Linux MMC List, open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, Prabhakar Hi Prabhakar, On Sun, May 3, 2020 at 11:48 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add support for iWave RZ/G1H Qseven System On Module. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Thanks for your patch! > --- /dev/null > +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi > @@ -0,0 +1,53 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for the iWave RZ/G1H Qseven SOM > + * > + * Copyright (C) 2020 Renesas Electronics Corp. > + */ > + > +#include "r8a7742.dtsi" > +#include <dt-bindings/gpio/gpio.h> > + > +/ { > + compatible = "iwave,g21m", "renesas,r8a7742"; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0 0x40000000 0 0x40000000>; > + }; > + > + memory@200000000 { > + device_type = "memory"; > + reg = <2 0x00000000 0 0x20000000>; According to the schematics, the second bank is also 1 GiB, so the reg length should be 0x40000000. > + }; > +&pfc { > + mmc1_pins: mmc1 { > + groups = "mmc1_data4", "mmc1_ctrl"; > + function = "mmc1"; > + }; > +}; > + > +&mmcif1 { > + pinctrl-0 = <&mmc1_pins>; > + pinctrl-names = "default"; > + > + vmmc-supply = <®_3p3v>; > + bus-width = <4>; > + non-removable; > + status = "okay"; > +}; The eMMC has an 8-bit data path. Is there any specific reason you use bus-width = <4>, and the "mmc1_data4" pin group? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 09/10] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM 2020-05-04 13:01 ` Geert Uytterhoeven @ 2020-05-04 14:20 ` Lad, Prabhakar 2020-05-04 14:29 ` Geert Uytterhoeven 0 siblings, 1 reply; 32+ messages in thread From: Lad, Prabhakar @ 2020-05-04 14:20 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, dmaengine, Linux MMC List, open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS Hi Geert, Thank you for the review. On Mon, May 4, 2020 at 2:01 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Sun, May 3, 2020 at 11:48 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Add support for iWave RZ/G1H Qseven System On Module. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi > > @@ -0,0 +1,53 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Device Tree Source for the iWave RZ/G1H Qseven SOM > > + * > > + * Copyright (C) 2020 Renesas Electronics Corp. > > + */ > > + > > +#include "r8a7742.dtsi" > > +#include <dt-bindings/gpio/gpio.h> > > + > > +/ { > > + compatible = "iwave,g21m", "renesas,r8a7742"; > > + > > + memory@40000000 { > > + device_type = "memory"; > > + reg = <0 0x40000000 0 0x40000000>; > > + }; > > + > > + memory@200000000 { > > + device_type = "memory"; > > + reg = <2 0x00000000 0 0x20000000>; > > According to the schematics, the second bank is also 1 GiB, so the > reg length should be 0x40000000. > Agreed will fix that. > > + }; > > > +&pfc { > > + mmc1_pins: mmc1 { > > + groups = "mmc1_data4", "mmc1_ctrl"; > > + function = "mmc1"; > > + }; > > +}; > > + > > +&mmcif1 { > > + pinctrl-0 = <&mmc1_pins>; > > + pinctrl-names = "default"; > > + > > + vmmc-supply = <®_3p3v>; > > + bus-width = <4>; > > + non-removable; > > + status = "okay"; > > +}; > > The eMMC has an 8-bit data path. Is there any specific reason you use > bus-width = <4>, and the "mmc1_data4" pin group? > MMC1_DATA7 is shared with VI1_CLK, so instead of limiting to only one device when using 8-bit just switched to 4bit mode so that both the peripherals can be used. Cheers, --Prabhakar > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 09/10] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM 2020-05-04 14:20 ` Lad, Prabhakar @ 2020-05-04 14:29 ` Geert Uytterhoeven 0 siblings, 0 replies; 32+ messages in thread From: Geert Uytterhoeven @ 2020-05-04 14:29 UTC (permalink / raw) To: Lad, Prabhakar Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, dmaengine, Linux MMC List, open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS Hi Prabhakar, On Mon, May 4, 2020 at 4:20 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Mon, May 4, 2020 at 2:01 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Sun, May 3, 2020 at 11:48 PM Lad Prabhakar > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > Add support for iWave RZ/G1H Qseven System On Module. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > > --- /dev/null > > > +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi > > > @@ -0,0 +1,53 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +/* > > > + * Device Tree Source for the iWave RZ/G1H Qseven SOM > > > + * > > > + * Copyright (C) 2020 Renesas Electronics Corp. > > > + */ > > > + > > > +#include "r8a7742.dtsi" > > > +#include <dt-bindings/gpio/gpio.h> > > > + > > > +/ { > > > + compatible = "iwave,g21m", "renesas,r8a7742"; > > > + > > > + memory@40000000 { > > > + device_type = "memory"; > > > + reg = <0 0x40000000 0 0x40000000>; > > > + }; > > > + > > > + memory@200000000 { > > > + device_type = "memory"; > > > + reg = <2 0x00000000 0 0x20000000>; > > > > According to the schematics, the second bank is also 1 GiB, so the > > reg length should be 0x40000000. > > > Agreed will fix that. Thanks for the confirmation. I can fix that while applying. > > > + }; > > > > > +&pfc { > > > + mmc1_pins: mmc1 { > > > + groups = "mmc1_data4", "mmc1_ctrl"; > > > + function = "mmc1"; > > > + }; > > > +}; > > > + > > > +&mmcif1 { > > > + pinctrl-0 = <&mmc1_pins>; > > > + pinctrl-names = "default"; > > > + > > > + vmmc-supply = <®_3p3v>; > > > + bus-width = <4>; > > > + non-removable; > > > + status = "okay"; > > > +}; > > > > The eMMC has an 8-bit data path. Is there any specific reason you use > > bus-width = <4>, and the "mmc1_data4" pin group? > > > MMC1_DATA7 is shared with VI1_CLK, so instead of limiting to only one > device when using 8-bit just switched to 4bit mode so that both the > peripherals can be used. OK. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.8 with the above fixed. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 10/10] ARM: dts: r8a7742-iwg21d-q7: Add support for iWave G21D-Q7 board based on RZ/G1H 2020-05-03 21:46 [PATCH v2 00/10] Add initial support for R8A7742/RZG1H SoC and iW-RainboW-G21D-Qseven development board support Lad Prabhakar ` (8 preceding siblings ...) 2020-05-03 21:46 ` [PATCH v2 09/10] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM Lad Prabhakar @ 2020-05-03 21:46 ` Lad Prabhakar 2020-05-04 13:09 ` Geert Uytterhoeven 2020-06-05 12:51 ` Geert Uytterhoeven 9 siblings, 2 replies; 32+ messages in thread From: Lad Prabhakar @ 2020-05-03 21:46 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman Cc: linux-renesas-soc, devicetree, linux-kernel, dmaengine, linux-mmc, linux-gpio, linux-serial, Prabhakar, Lad Prabhakar Add support for iWave RainboW-G21D-Qseven board based on RZ/G1H. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 37 +++++++++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7742-iwg21d-q7.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e8dd99201397..ed3376cce638 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -917,6 +917,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r7s9210-rza2mevb.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7742-iwg21d-q7.dtb \ r8a7743-iwg20d-q7.dtb \ r8a7743-iwg20d-q7-dbcm-ca.dtb \ r8a7743-sk-rzg1m.dtb \ diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts new file mode 100644 index 000000000000..1f5c35c66d91 --- /dev/null +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ/G1H Qseven board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a7742-iwg21m.dtsi" + +/ { + model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H"; + compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; + + aliases { + serial2 = &scifa2; + }; + + chosen { + bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait"; + stdout-path = "serial2:115200n8"; + }; +}; + +&pfc { + scifa2_pins: scifa2 { + groups = "scifa2_data_c"; + function = "scifa2"; + }; +}; + +&scifa2 { + pinctrl-0 = <&scifa2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; -- 2.17.1 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2 10/10] ARM: dts: r8a7742-iwg21d-q7: Add support for iWave G21D-Q7 board based on RZ/G1H 2020-05-03 21:46 ` [PATCH v2 10/10] ARM: dts: r8a7742-iwg21d-q7: Add support for iWave G21D-Q7 board based on RZ/G1H Lad Prabhakar @ 2020-05-04 13:09 ` Geert Uytterhoeven 2020-06-05 12:51 ` Geert Uytterhoeven 1 sibling, 0 replies; 32+ messages in thread From: Geert Uytterhoeven @ 2020-05-04 13:09 UTC (permalink / raw) To: Lad Prabhakar Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, dmaengine, Linux MMC List, open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, Prabhakar On Sun, May 3, 2020 at 11:47 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add support for iWave RainboW-G21D-Qseven board based on RZ/G1H. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 10/10] ARM: dts: r8a7742-iwg21d-q7: Add support for iWave G21D-Q7 board based on RZ/G1H 2020-05-03 21:46 ` [PATCH v2 10/10] ARM: dts: r8a7742-iwg21d-q7: Add support for iWave G21D-Q7 board based on RZ/G1H Lad Prabhakar 2020-05-04 13:09 ` Geert Uytterhoeven @ 2020-06-05 12:51 ` Geert Uytterhoeven 2020-06-05 19:04 ` Lad, Prabhakar 1 sibling, 1 reply; 32+ messages in thread From: Geert Uytterhoeven @ 2020-06-05 12:51 UTC (permalink / raw) To: Lad Prabhakar Cc: Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, dmaengine, Linux MMC List, open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, Prabhakar Hi Prabhakar, On Sun, May 3, 2020 at 11:47 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add support for iWave RainboW-G21D-Qseven board based on RZ/G1H. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > --- /dev/null > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > @@ -0,0 +1,37 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for the iWave-RZ/G1H Qseven board > + * > + * Copyright (C) 2020 Renesas Electronics Corp. > + */ > + > +/dts-v1/; > +#include "r8a7742-iwg21m.dtsi" > + > +/ { > + model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H"; > + compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; > + > + aliases { > + serial2 = &scifa2; > + }; > + > + chosen { > + bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait"; > + stdout-path = "serial2:115200n8"; > + }; > +}; > + > +&pfc { > + scifa2_pins: scifa2 { > + groups = "scifa2_data_c"; Upon second look, I think this group is wrong. While labeled SCIFA2 in the SOM schematics, these signals seem to be connected to a debugging interface. The real UART2 seems to be present on the camera daughter board. Those signals are labeled "SCIFA2" in the camera board schematics, but "SCIF2" in the SOM schematics. This is OK, as "scif2_data" and "scifa2_data" share the same pins, so you can choose either SCIF2 or SCIFA2 to drive them. If I'm right, please change the group, and move all serial2 descriptions to the camera board DTS. > + function = "scifa2"; > + }; > +}; > + > +&scifa2 { > + pinctrl-0 = <&scifa2_pins>; > + pinctrl-names = "default"; > + > + status = "okay"; > +}; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 10/10] ARM: dts: r8a7742-iwg21d-q7: Add support for iWave G21D-Q7 board based on RZ/G1H 2020-06-05 12:51 ` Geert Uytterhoeven @ 2020-06-05 19:04 ` Lad, Prabhakar 0 siblings, 0 replies; 32+ messages in thread From: Lad, Prabhakar @ 2020-06-05 19:04 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Vinod Koul, Ulf Hansson, Linus Walleij, Greg Kroah-Hartman, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, dmaengine, Linux MMC List, open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS Hi Geert, On Fri, Jun 5, 2020 at 1:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Sun, May 3, 2020 at 11:47 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Add support for iWave RainboW-G21D-Qseven board based on RZ/G1H. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > > --- /dev/null > > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > > @@ -0,0 +1,37 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Device Tree Source for the iWave-RZ/G1H Qseven board > > + * > > + * Copyright (C) 2020 Renesas Electronics Corp. > > + */ > > + > > +/dts-v1/; > > +#include "r8a7742-iwg21m.dtsi" > > + > > +/ { > > + model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H"; > > + compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; > > + > > + aliases { > > + serial2 = &scifa2; > > + }; > > + > > + chosen { > > + bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait"; > > + stdout-path = "serial2:115200n8"; > > + }; > > +}; > > + > > +&pfc { > > + scifa2_pins: scifa2 { > > + groups = "scifa2_data_c"; > > Upon second look, I think this group is wrong. While labeled SCIFA2 in > the SOM schematics, these signals seem to be connected to a debugging > interface. > > The real UART2 seems to be present on the camera daughter board. Those > signals are labeled "SCIFA2" in the camera board schematics, but "SCIF2" > in the SOM schematics. This is OK, as "scif2_data" and "scifa2_data" > share the same pins, so you can choose either SCIF2 or SCIFA2 to drive > them. > > If I'm right, please change the group, and move all serial2 descriptions > to the camera board DTS. > I took a closer look at the schematics, SCIFA2 is connected to the debug interface similarly on G1M where SCIF0 is connected to the debug interface. I will send the user guide privately which should clarify the serial interfaces on the board. Cheers, --Prabhakar > > + function = "scifa2"; > > + }; > > +}; > > + > > +&scifa2 { > > + pinctrl-0 = <&scifa2_pins>; > > + pinctrl-names = "default"; > > + > > + status = "okay"; > > +}; > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds ^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2020-09-03 7:12 UTC | newest] Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-05-03 21:46 [PATCH v2 00/10] Add initial support for R8A7742/RZG1H SoC and iW-RainboW-G21D-Qseven development board support Lad Prabhakar 2020-05-03 21:46 ` [PATCH v2 01/10] dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support Lad Prabhakar 2020-05-12 22:17 ` Rob Herring 2020-05-03 21:46 ` [PATCH v2 02/10] pinctrl: sh-pfc: r8a7790: Add " Lad Prabhakar 2020-05-04 10:20 ` Geert Uytterhoeven 2020-05-04 13:41 ` Lad, Prabhakar 2020-05-03 21:46 ` [PATCH v2 03/10] dt-bindings: serial: renesas,scifa: Document r8a7742 bindings Lad Prabhakar 2020-05-12 22:20 ` Rob Herring 2020-05-28 19:36 ` Rob Herring 2020-05-03 21:46 ` [PATCH v2 04/10] dt-bindings: mmc: renesas,mmcif: Document r8a7742 DT bindings Lad Prabhakar 2020-05-04 10:26 ` Geert Uytterhoeven 2020-05-04 13:43 ` Lad, Prabhakar 2020-05-03 21:46 ` [PATCH v2 05/10] dt-bindings: renesas,rcar-dmac: Document r8a7742 support Lad Prabhakar 2020-05-12 22:21 ` Rob Herring 2020-08-27 11:08 ` Lad, Prabhakar 2020-09-03 7:12 ` Vinod Koul 2020-05-03 21:46 ` [PATCH v2 06/10] ARM: dts: r8a7742: Initial SoC device tree Lad Prabhakar 2020-05-04 10:28 ` Geert Uytterhoeven 2020-05-03 21:46 ` [PATCH v2 07/10] dt-bindings: arm: Document iW-RainboW-G21M-Qseven-RZG1H system on module Lad Prabhakar 2020-05-04 11:21 ` Geert Uytterhoeven 2020-05-12 22:21 ` Rob Herring 2020-05-03 21:46 ` [PATCH v2 08/10] dt-bindings: arm: Document iW-RainboW-G21D-Qseven-RZG1H board Lad Prabhakar 2020-05-04 11:21 ` Geert Uytterhoeven 2020-05-12 22:21 ` Rob Herring 2020-05-03 21:46 ` [PATCH v2 09/10] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM Lad Prabhakar 2020-05-04 13:01 ` Geert Uytterhoeven 2020-05-04 14:20 ` Lad, Prabhakar 2020-05-04 14:29 ` Geert Uytterhoeven 2020-05-03 21:46 ` [PATCH v2 10/10] ARM: dts: r8a7742-iwg21d-q7: Add support for iWave G21D-Q7 board based on RZ/G1H Lad Prabhakar 2020-05-04 13:09 ` Geert Uytterhoeven 2020-06-05 12:51 ` Geert Uytterhoeven 2020-06-05 19:04 ` Lad, Prabhakar
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