From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh+dt@kernel.org>, Vinod Koul <vkoul@kernel.org>,
Ulf Hansson <ulf.hansson@linaro.org>,
Linus Walleij <linus.walleij@linaro.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
dmaengine <dmaengine@vger.kernel.org>,
Linux MMC List <linux-mmc@vger.kernel.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
"open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org>,
Prabhakar <prabhakar.csengg@gmail.com>
Subject: Re: [PATCH v2 02/10] pinctrl: sh-pfc: r8a7790: Add r8a7742 PFC support
Date: Mon, 4 May 2020 12:20:33 +0200 [thread overview]
Message-ID: <CAMuHMdXruqw2pb3pfXNfxNgtc24FmVA376DLBQgubEYSGO7LSA@mail.gmail.com> (raw)
In-Reply-To: <1588542414-14826-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
Thanks for the update!
On Sun, May 3, 2020 at 11:47 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Renesas RZ/G1H (R8A7742) is pin compatible with R-Car H2 (R8A7790),
> however it doesn't have several automotive specific peripherals. Add
> a r8a7790 specific pin groups/functions along with common pin
s/a r8a7790/automotive/?
> groups/functions for supporting both r8a7790 and r8a7742 SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> @@ -5736,6 +5750,7 @@ static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
> .pin_to_pocctrl = r8a7790_pin_to_pocctrl,
> };
>
> +#ifdef CONFIG_PINCTRL_PFC_R8A7790
> const struct sh_pfc_soc_info r8a7790_pinmux_info = {
> .name = "r8a77900_pfc",
> .ops = &r8a7790_pinmux_ops,
> @@ -5745,13 +5760,38 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = {
>
> .pins = pinmux_pins,
> .nr_pins = ARRAY_SIZE(pinmux_pins),
> - .groups = pinmux_groups,
> - .nr_groups = ARRAY_SIZE(pinmux_groups),
> - .functions = pinmux_functions,
> - .nr_functions = ARRAY_SIZE(pinmux_functions),
> + .groups = pinmux_groups.common,
> + .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
> + ARRAY_SIZE(pinmux_groups.automotive),
> + .functions = pinmux_functions.common,
> + .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
> + ARRAY_SIZE(pinmux_functions.automotive),
> +
> + .cfg_regs = pinmux_config_regs,
> +
> + .pinmux_data = pinmux_data,
> + .pinmux_data_size = ARRAY_SIZE(pinmux_data),
> +};
> +#endif
> +
> +#ifdef CONFIG_PINCTRL_PFC_R8A7742
> +const struct sh_pfc_soc_info r8a7742_pinmux_info = {
> + .name = "r8a77420_pfc",
> + .ops = &r8a7790_pinmux_ops,
> + .unlock_reg = 0xe6060000, /* PMMR */
> +
> + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
> +
> + .pins = pinmux_pins,
> + .nr_pins = ARRAY_SIZE(pinmux_pins),
> + .groups = pinmux_groups.common,
> + .nr_groups = ARRAY_SIZE(pinmux_groups.common),
> + .functions = pinmux_functions.common,
> + .nr_functions = ARRAY_SIZE(pinmux_functions.common),
>
> .cfg_regs = pinmux_config_regs,
>
> .pinmux_data = pinmux_data,
> .pinmux_data_size = ARRAY_SIZE(pinmux_data),
> };
> +#endif
The r8a7742 section should be inserted before the r8a7790 section,
to preserve sort order.
No need to resend, will fix up while applying.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in sh-pfc-for-v5.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2020-05-04 10:20 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-03 21:46 [PATCH v2 00/10] Add initial support for R8A7742/RZG1H SoC and iW-RainboW-G21D-Qseven development board support Lad Prabhakar
2020-05-03 21:46 ` [PATCH v2 01/10] dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support Lad Prabhakar
2020-05-12 22:17 ` Rob Herring
2020-05-03 21:46 ` [PATCH v2 02/10] pinctrl: sh-pfc: r8a7790: Add " Lad Prabhakar
2020-05-04 10:20 ` Geert Uytterhoeven [this message]
2020-05-04 13:41 ` Lad, Prabhakar
2020-05-03 21:46 ` [PATCH v2 03/10] dt-bindings: serial: renesas,scifa: Document r8a7742 bindings Lad Prabhakar
2020-05-12 22:20 ` Rob Herring
2020-05-28 19:36 ` Rob Herring
2020-05-03 21:46 ` [PATCH v2 04/10] dt-bindings: mmc: renesas,mmcif: Document r8a7742 DT bindings Lad Prabhakar
2020-05-04 10:26 ` Geert Uytterhoeven
2020-05-04 13:43 ` Lad, Prabhakar
2020-05-03 21:46 ` [PATCH v2 05/10] dt-bindings: renesas,rcar-dmac: Document r8a7742 support Lad Prabhakar
2020-05-12 22:21 ` Rob Herring
2020-08-27 11:08 ` Lad, Prabhakar
2020-09-03 7:12 ` Vinod Koul
2020-05-03 21:46 ` [PATCH v2 06/10] ARM: dts: r8a7742: Initial SoC device tree Lad Prabhakar
2020-05-04 10:28 ` Geert Uytterhoeven
2020-05-03 21:46 ` [PATCH v2 07/10] dt-bindings: arm: Document iW-RainboW-G21M-Qseven-RZG1H system on module Lad Prabhakar
2020-05-04 11:21 ` Geert Uytterhoeven
2020-05-12 22:21 ` Rob Herring
2020-05-03 21:46 ` [PATCH v2 08/10] dt-bindings: arm: Document iW-RainboW-G21D-Qseven-RZG1H board Lad Prabhakar
2020-05-04 11:21 ` Geert Uytterhoeven
2020-05-12 22:21 ` Rob Herring
2020-05-03 21:46 ` [PATCH v2 09/10] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM Lad Prabhakar
2020-05-04 13:01 ` Geert Uytterhoeven
2020-05-04 14:20 ` Lad, Prabhakar
2020-05-04 14:29 ` Geert Uytterhoeven
2020-05-03 21:46 ` [PATCH v2 10/10] ARM: dts: r8a7742-iwg21d-q7: Add support for iWave G21D-Q7 board based on RZ/G1H Lad Prabhakar
2020-05-04 13:09 ` Geert Uytterhoeven
2020-06-05 12:51 ` Geert Uytterhoeven
2020-06-05 19:04 ` Lad, Prabhakar
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