Linux-Serial Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH 0/8] Add basic DT support for R8A774E1 SoC enabling HiHope RZ/G2H board
@ 2020-07-08 17:48 Lad Prabhakar
  2020-07-08 17:48 ` [PATCH 1/8] dt-bindings: serial: renesas,scif: Document r8a774e1 bindings Lad Prabhakar
                   ` (7 more replies)
  0 siblings, 8 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-07-08 17:48 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Thomas Gleixner,
	Jason Cooper, Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman,
	Catalin Marinas, Will Deacon
  Cc: linux-renesas-soc, devicetree, linux-mmc, linux-serial,
	linux-arm-kernel, linux-kernel, Prabhakar, Lad Prabhakar

Hi All,

This patch series adds basic SOC DT support for RZ/G2H and enabling
HiHope RZ/G2H board. With these minimalist DT the HiHope RZ/G2H
board can be booted from initramfs/eMMC.

This patch series is dependent [1].

[1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=314235

Cheers,
Prabhakar


Lad Prabhakar (3):
  dt-bindings: serial: renesas,scif: Document r8a774e1 bindings
  dt-bindings: serial: renesas,hscif: Document r8a774e1 bindings
  dt-bindings: mmc: renesas,sdhi: Add r8a774e1 support

Marian-Cristian Rotariu (5):
  dt-bindings: irqchip: renesas-irqc: Document r8a774e1 bindings
  arm64: defconfig: Enable R8A774E1 SoC
  arm64: dts: renesas: Initial r8a774e1 SoC device tree
  arm64: dts: renesas: Add HiHope RZ/G2H main board support
  arm64: dts: renesas: Add HiHope RZ/G2H sub board support

 .../interrupt-controller/renesas,irqc.yaml    |   1 +
 .../devicetree/bindings/mmc/renesas,sdhi.txt  |   1 +
 .../bindings/serial/renesas,hscif.yaml        |   1 +
 .../bindings/serial/renesas,scif.yaml         |   1 +
 arch/arm64/boot/dts/renesas/Makefile          |   2 +
 .../arm64/boot/dts/renesas/hihope-common.dtsi |   4 +-
 arch/arm64/boot/dts/renesas/hihope-rev4.dtsi  |   4 +-
 .../boot/dts/renesas/hihope-rzg2-ex.dtsi      |   2 +-
 .../dts/renesas/r8a774e1-hihope-rzg2h-ex.dts  |  15 +
 .../dts/renesas/r8a774e1-hihope-rzg2h.dts     |  26 +
 arch/arm64/boot/dts/renesas/r8a774e1.dtsi     | 652 ++++++++++++++++++
 arch/arm64/configs/defconfig                  |   1 +
 12 files changed, 705 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1.dtsi

-- 
2.17.1


^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 1/8] dt-bindings: serial: renesas,scif: Document r8a774e1 bindings
  2020-07-08 17:48 [PATCH 0/8] Add basic DT support for R8A774E1 SoC enabling HiHope RZ/G2H board Lad Prabhakar
@ 2020-07-08 17:48 ` Lad Prabhakar
  2020-07-13 11:23   ` Geert Uytterhoeven
  2020-07-20 22:20   ` [PATCH 1/8] dt-bindings: serial: renesas, scif: " Rob Herring
  2020-07-08 17:48 ` [PATCH 2/8] dt-bindings: serial: renesas,hscif: " Lad Prabhakar
                   ` (6 subsequent siblings)
  7 siblings, 2 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-07-08 17:48 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Thomas Gleixner,
	Jason Cooper, Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman,
	Catalin Marinas, Will Deacon
  Cc: linux-renesas-soc, devicetree, linux-mmc, linux-serial,
	linux-arm-kernel, linux-kernel, Prabhakar, Lad Prabhakar

RZ/G2H (R8A774E1) SoC also has the R-Car gen3 compatible SCIF ports,
so document the SoC specific bindings.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
index 570b379f9f19..f589ac7577ae 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
@@ -51,6 +51,7 @@ properties:
               - renesas,scif-r8a774a1     # RZ/G2M
               - renesas,scif-r8a774b1     # RZ/G2N
               - renesas,scif-r8a774c0     # RZ/G2E
+              - renesas,scif-r8a774e1     # RZ/G2H
               - renesas,scif-r8a7795      # R-Car H3
               - renesas,scif-r8a7796      # R-Car M3-W
               - renesas,scif-r8a77961     # R-Car M3-W+
-- 
2.17.1


^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 2/8] dt-bindings: serial: renesas,hscif: Document r8a774e1 bindings
  2020-07-08 17:48 [PATCH 0/8] Add basic DT support for R8A774E1 SoC enabling HiHope RZ/G2H board Lad Prabhakar
  2020-07-08 17:48 ` [PATCH 1/8] dt-bindings: serial: renesas,scif: Document r8a774e1 bindings Lad Prabhakar
@ 2020-07-08 17:48 ` Lad Prabhakar
  2020-07-13 11:24   ` Geert Uytterhoeven
  2020-07-20 22:20   ` [PATCH 2/8] dt-bindings: serial: renesas, hscif: " Rob Herring
  2020-07-08 17:48 ` [PATCH 3/8] dt-bindings: irqchip: renesas-irqc: " Lad Prabhakar
                   ` (5 subsequent siblings)
  7 siblings, 2 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-07-08 17:48 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Thomas Gleixner,
	Jason Cooper, Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman,
	Catalin Marinas, Will Deacon
  Cc: linux-renesas-soc, devicetree, linux-mmc, linux-serial,
	linux-arm-kernel, linux-kernel, Prabhakar, Lad Prabhakar

RZ/G2H (R8A774E1) SoC also has the R-Car gen3 compatible HSCIF ports,
so document the SoC specific bindings.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 Documentation/devicetree/bindings/serial/renesas,hscif.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml
index 6b04c0451d41..9fb87a648c1b 100644
--- a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml
@@ -42,6 +42,7 @@ properties:
               - renesas,hscif-r8a774a1     # RZ/G2M
               - renesas,hscif-r8a774b1     # RZ/G2N
               - renesas,hscif-r8a774c0     # RZ/G2E
+              - renesas,hscif-r8a774e1     # RZ/G2H
               - renesas,hscif-r8a7795      # R-Car H3
               - renesas,hscif-r8a7796      # R-Car M3-W
               - renesas,hscif-r8a77961     # R-Car M3-W+
-- 
2.17.1


^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 3/8] dt-bindings: irqchip: renesas-irqc: Document r8a774e1 bindings
  2020-07-08 17:48 [PATCH 0/8] Add basic DT support for R8A774E1 SoC enabling HiHope RZ/G2H board Lad Prabhakar
  2020-07-08 17:48 ` [PATCH 1/8] dt-bindings: serial: renesas,scif: Document r8a774e1 bindings Lad Prabhakar
  2020-07-08 17:48 ` [PATCH 2/8] dt-bindings: serial: renesas,hscif: " Lad Prabhakar
@ 2020-07-08 17:48 ` Lad Prabhakar
  2020-07-13 11:25   ` Geert Uytterhoeven
  2020-07-20 22:21   ` Rob Herring
  2020-07-08 17:48 ` [PATCH 4/8] dt-bindings: mmc: renesas,sdhi: Add r8a774e1 support Lad Prabhakar
                   ` (4 subsequent siblings)
  7 siblings, 2 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-07-08 17:48 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Thomas Gleixner,
	Jason Cooper, Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman,
	Catalin Marinas, Will Deacon
  Cc: linux-renesas-soc, devicetree, linux-mmc, linux-serial,
	linux-arm-kernel, linux-kernel, Prabhakar, Lad Prabhakar

From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>

Document SoC specific bindings for RZ/G2H (r8a774e1) SoC.

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../devicetree/bindings/interrupt-controller/renesas,irqc.yaml   | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml
index b67b8cbd33fc..9f3946a904e5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml
@@ -27,6 +27,7 @@ properties:
           - renesas,intc-ex-r8a774a1    # RZ/G2M
           - renesas,intc-ex-r8a774b1    # RZ/G2N
           - renesas,intc-ex-r8a774c0    # RZ/G2E
+          - renesas,intc-ex-r8a774e1    # RZ/G2H
           - renesas,intc-ex-r8a7795     # R-Car H3
           - renesas,intc-ex-r8a7796     # R-Car M3-W
           - renesas,intc-ex-r8a77965    # R-Car M3-N
-- 
2.17.1


^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 4/8] dt-bindings: mmc: renesas,sdhi: Add r8a774e1 support
  2020-07-08 17:48 [PATCH 0/8] Add basic DT support for R8A774E1 SoC enabling HiHope RZ/G2H board Lad Prabhakar
                   ` (2 preceding siblings ...)
  2020-07-08 17:48 ` [PATCH 3/8] dt-bindings: irqchip: renesas-irqc: " Lad Prabhakar
@ 2020-07-08 17:48 ` Lad Prabhakar
  2020-07-13 11:26   ` Geert Uytterhoeven
  2020-07-20 22:21   ` Rob Herring
  2020-07-08 17:48 ` [PATCH 5/8] arm64: defconfig: Enable R8A774E1 SoC Lad Prabhakar
                   ` (3 subsequent siblings)
  7 siblings, 2 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-07-08 17:48 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Thomas Gleixner,
	Jason Cooper, Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman,
	Catalin Marinas, Will Deacon
  Cc: linux-renesas-soc, devicetree, linux-mmc, linux-serial,
	linux-arm-kernel, linux-kernel, Prabhakar, Lad Prabhakar

Document SDHI controller for RZ/G2H (R8A774E1) SoC, which is compatible
with R-Car Gen3 SoC family.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
 Documentation/devicetree/bindings/mmc/renesas,sdhi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt b/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt
index 0ca9a622cce0..779e484fa3ef 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt
@@ -14,6 +14,7 @@ Required properties:
 		"renesas,sdhi-r8a774a1" - SDHI IP on R8A774A1 SoC
 		"renesas,sdhi-r8a774b1" - SDHI IP on R8A774B1 SoC
 		"renesas,sdhi-r8a774c0" - SDHI IP on R8A774C0 SoC
+		"renesas,sdhi-r8a774e1" - SDHI IP on R8A774E1 SoC
 		"renesas,sdhi-r8a77470" - SDHI IP on R8A77470 SoC
 		"renesas,sdhi-mmc-r8a77470" - SDHI/MMC IP on R8A77470 SoC
 		"renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC
-- 
2.17.1


^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 5/8] arm64: defconfig: Enable R8A774E1 SoC
  2020-07-08 17:48 [PATCH 0/8] Add basic DT support for R8A774E1 SoC enabling HiHope RZ/G2H board Lad Prabhakar
                   ` (3 preceding siblings ...)
  2020-07-08 17:48 ` [PATCH 4/8] dt-bindings: mmc: renesas,sdhi: Add r8a774e1 support Lad Prabhakar
@ 2020-07-08 17:48 ` Lad Prabhakar
  2020-07-13 11:28   ` Geert Uytterhoeven
  2020-07-08 17:48 ` [PATCH 6/8] arm64: dts: renesas: Initial r8a774e1 SoC device tree Lad Prabhakar
                   ` (2 subsequent siblings)
  7 siblings, 1 reply; 25+ messages in thread
From: Lad Prabhakar @ 2020-07-08 17:48 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Thomas Gleixner,
	Jason Cooper, Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman,
	Catalin Marinas, Will Deacon
  Cc: linux-renesas-soc, devicetree, linux-mmc, linux-serial,
	linux-arm-kernel, linux-kernel, Prabhakar, Lad Prabhakar

From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>

Enable the Renesas RZ/G2H (R8A774E1) SoC in the ARM64 defconfig.

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 89538d9e39e5..9f4856044060 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -875,6 +875,7 @@ CONFIG_QCOM_APR=m
 CONFIG_ARCH_R8A774A1=y
 CONFIG_ARCH_R8A774B1=y
 CONFIG_ARCH_R8A774C0=y
+CONFIG_ARCH_R8A774E1=y
 CONFIG_ARCH_R8A77950=y
 CONFIG_ARCH_R8A77951=y
 CONFIG_ARCH_R8A77960=y
-- 
2.17.1


^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 6/8] arm64: dts: renesas: Initial r8a774e1 SoC device tree
  2020-07-08 17:48 [PATCH 0/8] Add basic DT support for R8A774E1 SoC enabling HiHope RZ/G2H board Lad Prabhakar
                   ` (4 preceding siblings ...)
  2020-07-08 17:48 ` [PATCH 5/8] arm64: defconfig: Enable R8A774E1 SoC Lad Prabhakar
@ 2020-07-08 17:48 ` Lad Prabhakar
  2020-07-08 17:53   ` Marc Zyngier
                     ` (2 more replies)
  2020-07-08 17:48 ` [PATCH 7/8] arm64: dts: renesas: Add HiHope RZ/G2H main board support Lad Prabhakar
  2020-07-08 17:48 ` [PATCH 8/8] arm64: dts: renesas: Add HiHope RZ/G2H sub " Lad Prabhakar
  7 siblings, 3 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-07-08 17:48 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Thomas Gleixner,
	Jason Cooper, Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman,
	Catalin Marinas, Will Deacon
  Cc: linux-renesas-soc, devicetree, linux-mmc, linux-serial,
	linux-arm-kernel, linux-kernel, Prabhakar, Lad Prabhakar

From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>

Basic support for the RZ/G2H SoC.

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 652 ++++++++++++++++++++++
 1 file changed, 652 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
new file mode 100644
index 000000000000..6637e157ffcd
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -0,0 +1,652 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a774e1 SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
+#include <dt-bindings/power/r8a774e1-sysc.h>
+
+#define CPG_AUDIO_CLK_I		R8A774E1_CLK_S0D4
+
+/ {
+	compatible = "renesas,r8a774e1";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	/*
+	 * The external audio clocks are configured as 0 Hz fixed frequency
+	 * clocks by default.
+	 * Boards that provide audio clocks should override them.
+	 */
+	audio_clk_a: audio_clk_a {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	audio_clk_c: audio_clk_c {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&a57_0>;
+				};
+				core1 {
+					cpu = <&a57_1>;
+				};
+				core2 {
+					cpu = <&a57_2>;
+				};
+				core3 {
+					cpu = <&a57_3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&a53_0>;
+				};
+				core1 {
+					cpu = <&a53_1>;
+				};
+				core2 {
+					cpu = <&a53_2>;
+				};
+				core3 {
+					cpu = <&a53_3>;
+				};
+			};
+		};
+
+		a57_0: cpu@0 {
+			compatible = "arm,cortex-a57";
+			reg = <0x0>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;
+			next-level-cache = <&L2_CA57>;
+			enable-method = "psci";
+			dynamic-power-coefficient = <854>;
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
+			capacity-dmips-mhz = <1024>;
+			#cooling-cells = <2>;
+		};
+
+		a57_1: cpu@1 {
+			compatible = "arm,cortex-a57";
+			reg = <0x1>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;
+			next-level-cache = <&L2_CA57>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
+			capacity-dmips-mhz = <1024>;
+			#cooling-cells = <2>;
+		};
+
+		a57_2: cpu@2 {
+			compatible = "arm,cortex-a57";
+			reg = <0x2>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;
+			next-level-cache = <&L2_CA57>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
+			capacity-dmips-mhz = <1024>;
+			#cooling-cells = <2>;
+		};
+
+		a57_3: cpu@3 {
+			compatible = "arm,cortex-a57";
+			reg = <0x3>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;
+			next-level-cache = <&L2_CA57>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
+			capacity-dmips-mhz = <1024>;
+			#cooling-cells = <2>;
+		};
+
+		a53_0: cpu@100 {
+			compatible = "arm,cortex-a53";
+			reg = <0x100>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+			#cooling-cells = <2>;
+			dynamic-power-coefficient = <277>;
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
+			capacity-dmips-mhz = <535>;
+		};
+
+		a53_1: cpu@101 {
+			compatible = "arm,cortex-a53";
+			reg = <0x101>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
+			capacity-dmips-mhz = <535>;
+		};
+
+		a53_2: cpu@102 {
+			compatible = "arm,cortex-a53";
+			reg = <0x102>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
+			capacity-dmips-mhz = <535>;
+		};
+
+		a53_3: cpu@103 {
+			compatible = "arm,cortex-a53";
+			reg = <0x103>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
+			capacity-dmips-mhz = <535>;
+		};
+
+		L2_CA57: cache-controller-0 {
+			compatible = "cache";
+			power-domains = <&sysc R8A774E1_PD_CA57_SCU>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		L2_CA53: cache-controller-1 {
+			compatible = "cache";
+			power-domains = <&sysc R8A774E1_PD_CA53_SCU>;
+			cache-unified;
+			cache-level = <2>;
+		};
+	};
+
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	extalr_clk: extalr {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	/* External PCIe clock - can be overridden by the board */
+	pcie_bus_clk: pcie_bus {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	pmu_a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
+	};
+
+	pmu_a57 {
+		compatible = "arm,cortex-a57-pmu";
+		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	/* External SCIF clock - to be overridden by boards that provide it */
+	scif_clk: scif {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		rwdt: watchdog@e6020000 {
+			reg = <0 0xe6020000 0 0x0c>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		gpio0: gpio@e6050000 {
+			reg = <0 0xe6050000 0 0x50>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			/* placeholder */
+		};
+
+		gpio1: gpio@e6051000 {
+			reg = <0 0xe6051000 0 0x50>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			/* placeholder */
+		};
+
+		gpio2: gpio@e6052000 {
+			reg = <0 0xe6052000 0 0x50>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			/* placeholder */
+		};
+
+		gpio3: gpio@e6053000 {
+			/* placeholder */
+			reg = <0 0xe6053000 0 0x50>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			/* placeholder */
+		};
+
+		gpio4: gpio@e6054000 {
+			reg = <0 0xe6054000 0 0x50>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			/* placeholder */
+		};
+
+		gpio5: gpio@e6055000 {
+			reg = <0 0xe6055000 0 0x50>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			/* placeholder */
+		};
+
+		gpio6: gpio@e6055400 {
+			reg = <0 0xe6055400 0 0x50>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			/* placeholder */
+		};
+
+		gpio7: gpio@e6055800 {
+			reg = <0 0xe6055800 0 0x50>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			/* placeholder */
+		};
+
+		pfc: pin-controller@e6060000 {
+			compatible = "renesas,pfc-r8a774e1";
+			reg = <0 0xe6060000 0 0x50c>;
+		};
+
+		cpg: clock-controller@e6150000 {
+			compatible = "renesas,r8a774e1-cpg-mssr";
+			reg = <0 0xe6150000 0 0x1000>;
+			clocks = <&extal_clk>, <&extalr_clk>;
+			clock-names = "extal", "extalr";
+			#clock-cells = <2>;
+			#power-domain-cells = <0>;
+			#reset-cells = <1>;
+		};
+
+		rst: reset-controller@e6160000 {
+			compatible = "renesas,r8a774e1-rst";
+			reg = <0 0xe6160000 0 0x0200>;
+		};
+
+		sysc: system-controller@e6180000 {
+			compatible = "renesas,r8a774e1-sysc";
+			reg = <0 0xe6180000 0 0x0400>;
+			#power-domain-cells = <1>;
+		};
+
+		intc_ex: interrupt-controller@e61c0000 {
+			compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0 0xe61c0000 0 0x200>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 407>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 407>;
+		};
+
+		i2c2: i2c@e6510000 {
+			reg = <0 0xe6510000 0 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		i2c4: i2c@e66d8000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0xe66d8000 0 0x40>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		hscif0: serial@e6540000 {
+			reg = <0 0xe6540000 0 0x60>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		hsusb: usb@e6590000 {
+			reg = <0 0xe6590000 0 0x200>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		usb3_phy0: usb-phy@e65ee000 {
+			reg = <0 0xe65ee000 0 0x90>;
+			#phy-cells = <0>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		avb: ethernet@e6800000 {
+			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		can0: can@e6c30000 {
+			reg = <0 0xe6c30000 0 0x1000>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		can1: can@e6c38000 {
+			reg = <0 0xe6c38000 0 0x1000>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		pwm0: pwm@e6e30000 {
+			reg = <0 0xe6e30000 0 0x8>;
+			#pwm-cells = <2>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		scif2: serial@e6e88000 {
+			compatible = "renesas,scif-r8a774e1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e88000 0 0x40>;
+			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 310>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 310>;
+			status = "disabled";
+		};
+
+		rcar_sound: sound@ec500000 {
+			reg = <0 0xec500000 0 0x1000>, /* SCU */
+			      <0 0xec5a0000 0 0x100>,  /* ADG */
+			      <0 0xec540000 0 0x1000>, /* SSIU */
+			      <0 0xec541000 0 0x280>,  /* SSI */
+			      <0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
+			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+			status = "disabled";
+
+			/* placeholder */
+
+			rcar_sound,ssi {
+				ssi2: ssi-2 {
+					/* placeholder */
+				};
+			};
+		};
+
+		xhci0: usb@ee000000 {
+			reg = <0 0xee000000 0 0xc00>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		usb3_peri0: usb@ee020000 {
+			reg = <0 0xee020000 0 0x400>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		ohci0: usb@ee080000 {
+			reg = <0 0xee080000 0 0x100>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		ohci1: usb@ee0a0000 {
+			reg = <0 0xee0a0000 0 0x100>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		ehci0: usb@ee080100 {
+			reg = <0 0xee080100 0 0x100>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		ehci1: usb@ee0a0100 {
+			reg = <0 0xee0a0100 0 0x100>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		usb2_phy0: usb-phy@ee080200 {
+			reg = <0 0xee080200 0 0x700>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		usb2_phy1: usb-phy@ee0a0200 {
+			reg = <0 0xee0a0200 0 0x700>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		sdhi0: sd@ee100000 {
+			reg = <0 0xee100000 0 0x2000>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		sdhi2: sd@ee140000 {
+			reg = <0 0xee140000 0 0x2000>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		sdhi3: sd@ee160000 {
+			compatible = "renesas,sdhi-r8a774e1",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee160000 0 0x2000>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 311>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 311>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@f1010000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x0 0xf1010000 0 0x1000>,
+			      <0x0 0xf1020000 0 0x20000>,
+			      <0x0 0xf1040000 0 0x20000>,
+			      <0x0 0xf1060000 0 0x20000>;
+			interrupts = <GIC_PPI 9
+					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+			clocks = <&cpg CPG_MOD 408>;
+			clock-names = "clk";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 408>;
+		};
+
+		pciec0: pcie@fe000000 {
+			reg = <0 0xfe000000 0 0x80000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		hdmi0: hdmi@fead0000 {
+			reg = <0 0xfead0000 0 0x10000>;
+			status = "disabled";
+
+			/* placeholder */
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+				port@1 {
+					reg = <1>;
+				};
+				port@2 {
+					reg = <2>;
+				};
+			};
+		};
+
+		du: display@feb00000 {
+			reg = <0 0xfeb00000 0 0x80000>;
+			status = "disabled";
+
+			/* placeholder */
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+				port@1 {
+					reg = <1>;
+				};
+				port@2 {
+					reg = <2>;
+				};
+			};
+		};
+
+		prr: chipid@fff00044 {
+			compatible = "renesas,prr";
+			reg = <0 0xfff00044 0 4>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	/* External USB clocks - can be overridden by the board */
+	usb3s0_clk: usb3s0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	usb_extal_clk: usb_extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+};
-- 
2.17.1


^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 7/8] arm64: dts: renesas: Add HiHope RZ/G2H main board support
  2020-07-08 17:48 [PATCH 0/8] Add basic DT support for R8A774E1 SoC enabling HiHope RZ/G2H board Lad Prabhakar
                   ` (5 preceding siblings ...)
  2020-07-08 17:48 ` [PATCH 6/8] arm64: dts: renesas: Initial r8a774e1 SoC device tree Lad Prabhakar
@ 2020-07-08 17:48 ` Lad Prabhakar
  2020-07-13 12:25   ` Geert Uytterhoeven
  2020-07-08 17:48 ` [PATCH 8/8] arm64: dts: renesas: Add HiHope RZ/G2H sub " Lad Prabhakar
  7 siblings, 1 reply; 25+ messages in thread
From: Lad Prabhakar @ 2020-07-08 17:48 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Thomas Gleixner,
	Jason Cooper, Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman,
	Catalin Marinas, Will Deacon
  Cc: linux-renesas-soc, devicetree, linux-mmc, linux-serial,
	linux-arm-kernel, linux-kernel, Prabhakar, Lad Prabhakar

From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>

Basic support for the HiHope RZ/G2H main board:
  - Memory,
  - Main crystal,
  - Serial console
  - eMMC

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile          |  1 +
 .../arm64/boot/dts/renesas/hihope-common.dtsi |  4 +--
 arch/arm64/boot/dts/renesas/hihope-rev4.dtsi  |  4 +--
 .../dts/renesas/r8a774e1-hihope-rzg2h.dts     | 26 +++++++++++++++++++
 4 files changed, 31 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 21cc63469082..0688125f8fbf 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb \
 dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb \
 			       r8a774c0-ek874-idk-2121wr.dtb \
 			       r8a774c0-ek874-mipi-2.1.dtb
+dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb
 dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb
 dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb r8a77950-ulcb-kf.dtb
 dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x.dtb r8a77951-salvator-xs.dtb
diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
index beddfd7a7584..2eda9f66ae81 100644
--- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the HiHope RZ/G2[MN] main board
- * Rev.[2.0/3.0/4.0] common parts
+ * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
+ * HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts
  *
  * Copyright (C) 2019 Renesas Electronics Corp.
  */
diff --git a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi
index 9f869187aea6..3046c07a288b 100644
--- a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the HiHope RZ/G2[MN] Rev.3.0/4.0 main board
- * common parts
+ * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
+ * HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts
  *
  * Copyright (C) 2020 Renesas Electronics Corp.
  */
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts
new file mode 100644
index 000000000000..cdbe527e9340
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H main board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774e1.dtsi"
+#include "hihope-rev4.dtsi"
+
+/ {
+	model = "HopeRun HiHope RZ/G2H main board based on r8a774e1";
+	compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x78000000>;
+	};
+
+	memory@500000000 {
+		device_type = "memory";
+		reg = <0x5 0x00000000 0x0 0x80000000>;
+	};
+};
-- 
2.17.1


^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 8/8] arm64: dts: renesas: Add HiHope RZ/G2H sub board support
  2020-07-08 17:48 [PATCH 0/8] Add basic DT support for R8A774E1 SoC enabling HiHope RZ/G2H board Lad Prabhakar
                   ` (6 preceding siblings ...)
  2020-07-08 17:48 ` [PATCH 7/8] arm64: dts: renesas: Add HiHope RZ/G2H main board support Lad Prabhakar
@ 2020-07-08 17:48 ` Lad Prabhakar
  2020-07-13 12:25   ` Geert Uytterhoeven
  7 siblings, 1 reply; 25+ messages in thread
From: Lad Prabhakar @ 2020-07-08 17:48 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Thomas Gleixner,
	Jason Cooper, Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman,
	Catalin Marinas, Will Deacon
  Cc: linux-renesas-soc, devicetree, linux-mmc, linux-serial,
	linux-arm-kernel, linux-kernel, Prabhakar, Lad Prabhakar

From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>

The HiHope RZ/G2H sub board sits below the HiHope RZ/G2H main board.
These boards are identical with the ones for RZ/G2M[N].

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile              |  3 ++-
 arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi   |  2 +-
 .../boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts | 15 +++++++++++++++
 3 files changed, 18 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 0688125f8fbf..19b7d7cfa22f 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -14,7 +14,8 @@ dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb \
 dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb \
 			       r8a774c0-ek874-idk-2121wr.dtb \
 			       r8a774c0-ek874-mipi-2.1.dtb
-dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb
+dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb \
+			       r8a774e1-hihope-rzg2h-ex.dtb
 dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb
 dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb r8a77950-ulcb-kf.dtb
 dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x.dtb r8a77951-salvator-xs.dtb
diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
index acfcfd050a6c..178401a34cbf 100644
--- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the RZ/G2[MN] HiHope sub board common parts
+ * Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts
  *
  * Copyright (C) 2019 Renesas Electronics Corp.
  */
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts
new file mode 100644
index 000000000000..265355e0de5f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H sub board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-hihope-rzg2h.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+	model = "HopeRun HiHope RZ/G2H with sub board";
+	compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
+		     "renesas,r8a774e1";
+};
-- 
2.17.1


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 6/8] arm64: dts: renesas: Initial r8a774e1 SoC device tree
  2020-07-08 17:48 ` [PATCH 6/8] arm64: dts: renesas: Initial r8a774e1 SoC device tree Lad Prabhakar
@ 2020-07-08 17:53   ` Marc Zyngier
  2020-07-08 18:07     ` Lad, Prabhakar
  2020-07-13 12:24   ` Geert Uytterhoeven
  2020-07-16 14:50   ` Geert Uytterhoeven
  2 siblings, 1 reply; 25+ messages in thread
From: Marc Zyngier @ 2020-07-08 17:53 UTC (permalink / raw)
  To: Lad Prabhakar
  Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Thomas Gleixner,
	Jason Cooper, Ulf Hansson, Greg Kroah-Hartman, Catalin Marinas,
	Will Deacon, linux-renesas-soc, devicetree, linux-mmc,
	linux-serial, linux-arm-kernel, linux-kernel, Prabhakar

On 2020-07-08 18:48, Lad Prabhakar wrote:
> From: Marian-Cristian Rotariu 
> <marian-cristian.rotariu.rb@bp.renesas.com>
> 
> Basic support for the RZ/G2H SoC.
> 
> Signed-off-by: Marian-Cristian Rotariu
> <marian-cristian.rotariu.rb@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 652 ++++++++++++++++++++++
>  1 file changed, 652 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> new file mode 100644
> index 000000000000..6637e157ffcd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi

[...]
> +		gic: interrupt-controller@f1010000 {
> +			compatible = "arm,gic-400";
> +			#interrupt-cells = <3>;
> +			#address-cells = <0>;
> +			interrupt-controller;
> +			reg = <0x0 0xf1010000 0 0x1000>,
> +			      <0x0 0xf1020000 0 0x20000>,
> +			      <0x0 0xf1040000 0 0x20000>,
> +			      <0x0 0xf1060000 0 0x20000>;
> +			interrupts = <GIC_PPI 9
> +					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;

You seem to have a bit more than only 2 CPUs in this system.

> +			clocks = <&cpg CPG_MOD 408>;
> +			clock-names = "clk";
> +			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
> +			resets = <&cpg 408>;
> +		};

         M.
-- 
Jazz is not dead. It just smells funny...

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 6/8] arm64: dts: renesas: Initial r8a774e1 SoC device tree
  2020-07-08 17:53   ` Marc Zyngier
@ 2020-07-08 18:07     ` Lad, Prabhakar
  0 siblings, 0 replies; 25+ messages in thread
From: Lad, Prabhakar @ 2020-07-08 18:07 UTC (permalink / raw)
  To: Marc Zyngier
  Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
	Thomas Gleixner, Jason Cooper, Ulf Hansson, Greg Kroah-Hartman,
	Catalin Marinas, Will Deacon, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Linux MMC List, open list:SERIAL DRIVERS, LAK, LKML

Hi Marc,

Thank you for the review.

On Wed, Jul 8, 2020 at 6:53 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On 2020-07-08 18:48, Lad Prabhakar wrote:
> > From: Marian-Cristian Rotariu
> > <marian-cristian.rotariu.rb@bp.renesas.com>
> >
> > Basic support for the RZ/G2H SoC.
> >
> > Signed-off-by: Marian-Cristian Rotariu
> > <marian-cristian.rotariu.rb@bp.renesas.com>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >  arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 652 ++++++++++++++++++++++
> >  1 file changed, 652 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> > b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> > new file mode 100644
> > index 000000000000..6637e157ffcd
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
>
> [...]
> > +             gic: interrupt-controller@f1010000 {
> > +                     compatible = "arm,gic-400";
> > +                     #interrupt-cells = <3>;
> > +                     #address-cells = <0>;
> > +                     interrupt-controller;
> > +                     reg = <0x0 0xf1010000 0 0x1000>,
> > +                           <0x0 0xf1020000 0 0x20000>,
> > +                           <0x0 0xf1040000 0 0x20000>,
> > +                           <0x0 0xf1060000 0 0x20000>;
> > +                     interrupts = <GIC_PPI 9
> > +                                     (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
>
> You seem to have a bit more than only 2 CPUs in this system.
>
Argh should be 8.

Cheers,
--Prabhakar

> > +                     clocks = <&cpg CPG_MOD 408>;
> > +                     clock-names = "clk";
> > +                     power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
> > +                     resets = <&cpg 408>;
> > +             };
>
>          M.
> --
> Jazz is not dead. It just smells funny...

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 1/8] dt-bindings: serial: renesas,scif: Document r8a774e1 bindings
  2020-07-08 17:48 ` [PATCH 1/8] dt-bindings: serial: renesas,scif: Document r8a774e1 bindings Lad Prabhakar
@ 2020-07-13 11:23   ` Geert Uytterhoeven
  2020-07-20 22:20   ` [PATCH 1/8] dt-bindings: serial: renesas, scif: " Rob Herring
  1 sibling, 0 replies; 25+ messages in thread
From: Geert Uytterhoeven @ 2020-07-13 11:23 UTC (permalink / raw)
  To: Lad Prabhakar
  Cc: Magnus Damm, Rob Herring, Thomas Gleixner, Jason Cooper,
	Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman, Catalin Marinas,
	Will Deacon, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Linux MMC List, open list:SERIAL DRIVERS, Linux ARM,
	Linux Kernel Mailing List, Prabhakar

On Wed, Jul 8, 2020 at 7:48 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> RZ/G2H (R8A774E1) SoC also has the R-Car gen3 compatible SCIF ports,
> so document the SoC specific bindings.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 2/8] dt-bindings: serial: renesas,hscif: Document r8a774e1 bindings
  2020-07-08 17:48 ` [PATCH 2/8] dt-bindings: serial: renesas,hscif: " Lad Prabhakar
@ 2020-07-13 11:24   ` Geert Uytterhoeven
  2020-07-20 22:20   ` [PATCH 2/8] dt-bindings: serial: renesas, hscif: " Rob Herring
  1 sibling, 0 replies; 25+ messages in thread
From: Geert Uytterhoeven @ 2020-07-13 11:24 UTC (permalink / raw)
  To: Lad Prabhakar
  Cc: Magnus Damm, Rob Herring, Thomas Gleixner, Jason Cooper,
	Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman, Catalin Marinas,
	Will Deacon, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Linux MMC List, open list:SERIAL DRIVERS, Linux ARM,
	Linux Kernel Mailing List, Prabhakar

On Wed, Jul 8, 2020 at 7:48 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> RZ/G2H (R8A774E1) SoC also has the R-Car gen3 compatible HSCIF ports,
> so document the SoC specific bindings.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 3/8] dt-bindings: irqchip: renesas-irqc: Document r8a774e1 bindings
  2020-07-08 17:48 ` [PATCH 3/8] dt-bindings: irqchip: renesas-irqc: " Lad Prabhakar
@ 2020-07-13 11:25   ` Geert Uytterhoeven
  2020-07-20 22:21   ` Rob Herring
  1 sibling, 0 replies; 25+ messages in thread
From: Geert Uytterhoeven @ 2020-07-13 11:25 UTC (permalink / raw)
  To: Lad Prabhakar
  Cc: Magnus Damm, Rob Herring, Thomas Gleixner, Jason Cooper,
	Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman, Catalin Marinas,
	Will Deacon, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Linux MMC List, open list:SERIAL DRIVERS, Linux ARM,
	Linux Kernel Mailing List, Prabhakar

On Wed, Jul 8, 2020 at 7:48 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
>
> Document SoC specific bindings for RZ/G2H (r8a774e1) SoC.
>
> Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 4/8] dt-bindings: mmc: renesas,sdhi: Add r8a774e1 support
  2020-07-08 17:48 ` [PATCH 4/8] dt-bindings: mmc: renesas,sdhi: Add r8a774e1 support Lad Prabhakar
@ 2020-07-13 11:26   ` Geert Uytterhoeven
  2020-07-20 22:21   ` Rob Herring
  1 sibling, 0 replies; 25+ messages in thread
From: Geert Uytterhoeven @ 2020-07-13 11:26 UTC (permalink / raw)
  To: Lad Prabhakar
  Cc: Magnus Damm, Rob Herring, Thomas Gleixner, Jason Cooper,
	Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman, Catalin Marinas,
	Will Deacon, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Linux MMC List, open list:SERIAL DRIVERS, Linux ARM,
	Linux Kernel Mailing List, Prabhakar

On Wed, Jul 8, 2020 at 7:48 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Document SDHI controller for RZ/G2H (R8A774E1) SoC, which is compatible
> with R-Car Gen3 SoC family.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 5/8] arm64: defconfig: Enable R8A774E1 SoC
  2020-07-08 17:48 ` [PATCH 5/8] arm64: defconfig: Enable R8A774E1 SoC Lad Prabhakar
@ 2020-07-13 11:28   ` Geert Uytterhoeven
  0 siblings, 0 replies; 25+ messages in thread
From: Geert Uytterhoeven @ 2020-07-13 11:28 UTC (permalink / raw)
  To: Lad Prabhakar
  Cc: Magnus Damm, Rob Herring, Thomas Gleixner, Jason Cooper,
	Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman, Catalin Marinas,
	Will Deacon, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Linux MMC List, open list:SERIAL DRIVERS, Linux ARM,
	Linux Kernel Mailing List, Prabhakar

On Wed, Jul 8, 2020 at 7:48 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
>
> Enable the Renesas RZ/G2H (R8A774E1) SoC in the ARM64 defconfig.
>
> Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.9.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 6/8] arm64: dts: renesas: Initial r8a774e1 SoC device tree
  2020-07-08 17:48 ` [PATCH 6/8] arm64: dts: renesas: Initial r8a774e1 SoC device tree Lad Prabhakar
  2020-07-08 17:53   ` Marc Zyngier
@ 2020-07-13 12:24   ` Geert Uytterhoeven
  2020-07-16 14:50   ` Geert Uytterhoeven
  2 siblings, 0 replies; 25+ messages in thread
From: Geert Uytterhoeven @ 2020-07-13 12:24 UTC (permalink / raw)
  To: Lad Prabhakar
  Cc: Magnus Damm, Rob Herring, Thomas Gleixner, Jason Cooper,
	Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman, Catalin Marinas,
	Will Deacon, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Linux MMC List, open list:SERIAL DRIVERS, Linux ARM,
	Linux Kernel Mailing List, Prabhakar

Hi Prabhakar,

On Wed, Jul 8, 2020 at 7:49 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
>
> Basic support for the RZ/G2H SoC.
>
> Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi

> +               avb: ethernet@e6800000 {
> +                       reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;

According to Rev. 1.00 of the Hardware User's Manual, RZ/G2H does not
have the Stream Buffer for EtherAVB-IF, so the second register block
should be dropped.

> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +
> +                       /* placeholder */
> +               };

> +               gic: interrupt-controller@f1010000 {
> +                       compatible = "arm,gic-400";
> +                       #interrupt-cells = <3>;
> +                       #address-cells = <0>;
> +                       interrupt-controller;
> +                       reg = <0x0 0xf1010000 0 0x1000>,
> +                             <0x0 0xf1020000 0 0x20000>,
> +                             <0x0 0xf1040000 0 0x20000>,
> +                             <0x0 0xf1060000 0 0x20000>;
> +                       interrupts = <GIC_PPI 9
> +                                       (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;

Like Marc already pointed out, GIC_CPU_MASK_SIMPLE(8).

With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Will queue in renesas-devel for v5.9, after fixing the above.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 7/8] arm64: dts: renesas: Add HiHope RZ/G2H main board support
  2020-07-08 17:48 ` [PATCH 7/8] arm64: dts: renesas: Add HiHope RZ/G2H main board support Lad Prabhakar
@ 2020-07-13 12:25   ` Geert Uytterhoeven
  0 siblings, 0 replies; 25+ messages in thread
From: Geert Uytterhoeven @ 2020-07-13 12:25 UTC (permalink / raw)
  To: Lad Prabhakar
  Cc: Magnus Damm, Rob Herring, Thomas Gleixner, Jason Cooper,
	Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman, Catalin Marinas,
	Will Deacon, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Linux MMC List, open list:SERIAL DRIVERS, Linux ARM,
	Linux Kernel Mailing List, Prabhakar

On Wed, Jul 8, 2020 at 7:49 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
>
> Basic support for the HiHope RZ/G2H main board:
>   - Memory,
>   - Main crystal,
>   - Serial console
>   - eMMC
>
> Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.9.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 8/8] arm64: dts: renesas: Add HiHope RZ/G2H sub board support
  2020-07-08 17:48 ` [PATCH 8/8] arm64: dts: renesas: Add HiHope RZ/G2H sub " Lad Prabhakar
@ 2020-07-13 12:25   ` Geert Uytterhoeven
  0 siblings, 0 replies; 25+ messages in thread
From: Geert Uytterhoeven @ 2020-07-13 12:25 UTC (permalink / raw)
  To: Lad Prabhakar
  Cc: Magnus Damm, Rob Herring, Thomas Gleixner, Jason Cooper,
	Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman, Catalin Marinas,
	Will Deacon, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Linux MMC List, open list:SERIAL DRIVERS, Linux ARM,
	Linux Kernel Mailing List, Prabhakar

On Wed, Jul 8, 2020 at 7:49 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
>
> The HiHope RZ/G2H sub board sits below the HiHope RZ/G2H main board.
> These boards are identical with the ones for RZ/G2M[N].
>
> Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.9.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 6/8] arm64: dts: renesas: Initial r8a774e1 SoC device tree
  2020-07-08 17:48 ` [PATCH 6/8] arm64: dts: renesas: Initial r8a774e1 SoC device tree Lad Prabhakar
  2020-07-08 17:53   ` Marc Zyngier
  2020-07-13 12:24   ` Geert Uytterhoeven
@ 2020-07-16 14:50   ` Geert Uytterhoeven
  2020-07-16 16:50     ` Prabhakar Mahadev Lad
  2 siblings, 1 reply; 25+ messages in thread
From: Geert Uytterhoeven @ 2020-07-16 14:50 UTC (permalink / raw)
  To: Lad Prabhakar
  Cc: Magnus Damm, Rob Herring, Thomas Gleixner, Jason Cooper,
	Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman, Catalin Marinas,
	Will Deacon, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Linux MMC List, open list:SERIAL DRIVERS, Linux ARM,
	Linux Kernel Mailing List, Prabhakar

Hi Prabhakar,

On Wed, Jul 8, 2020 at 7:49 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
>
> Basic support for the RZ/G2H SoC.
>
> Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 652 ++++++++++++++++++++++
>  1 file changed, 652 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1.dtsi
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> new file mode 100644
> index 000000000000..6637e157ffcd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi

> +               intc_ex: interrupt-controller@e61c0000 {
> +                       compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc";

Woops, '4e1, of course.

As I haven't sent a PR for arm-soc yet, I'll fix it up in renesas-devel.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 25+ messages in thread

* RE: [PATCH 6/8] arm64: dts: renesas: Initial r8a774e1 SoC device tree
  2020-07-16 14:50   ` Geert Uytterhoeven
@ 2020-07-16 16:50     ` Prabhakar Mahadev Lad
  0 siblings, 0 replies; 25+ messages in thread
From: Prabhakar Mahadev Lad @ 2020-07-16 16:50 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Magnus Damm, Rob Herring, Thomas Gleixner, Jason Cooper,
	Marc Zyngier, Ulf Hansson, Greg Kroah-Hartman, Catalin Marinas,
	Will Deacon, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Linux MMC List, open list:SERIAL DRIVERS, Linux ARM,
	Linux Kernel Mailing List, Prabhakar

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 16 July 2020 15:51
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: Magnus Damm <magnus.damm@gmail.com>; Rob Herring <robh+dt@kernel.org>; Thomas Gleixner <tglx@linutronix.de>; Jason
> Cooper <jason@lakedaemon.net>; Marc Zyngier <maz@kernel.org>; Ulf Hansson <ulf.hansson@linaro.org>; Greg Kroah-Hartman
> <gregkh@linuxfoundation.org>; Catalin Marinas <catalin.marinas@arm.com>; Will Deacon <will@kernel.org>; Linux-Renesas <linux-
> renesas-soc@vger.kernel.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; Linux
> MMC List <linux-mmc@vger.kernel.org>; open list:SERIAL DRIVERS <linux-serial@vger.kernel.org>; Linux ARM <linux-arm-
> kernel@lists.infradead.org>; Linux Kernel Mailing List <linux-kernel@vger.kernel.org>; Prabhakar <prabhakar.csengg@gmail.com>
> Subject: Re: [PATCH 6/8] arm64: dts: renesas: Initial r8a774e1 SoC device tree
>
> Hi Prabhakar,
>
> On Wed, Jul 8, 2020 at 7:49 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> >
> > Basic support for the RZ/G2H SoC.
> >
> > Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >  arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 652 ++++++++++++++++++++++
> >  1 file changed, 652 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> > new file mode 100644
> > index 000000000000..6637e157ffcd
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
>
> > +               intc_ex: interrupt-controller@e61c0000 {
> > +                       compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc";
>
> Woops, '4e1, of course.
>
> As I haven't sent a PR for arm-soc yet, I'll fix it up in renesas-devel.
>
Argh, thanks for the catch.

Cheers,
--Prabhakar

> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds


Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 1/8] dt-bindings: serial: renesas, scif: Document r8a774e1 bindings
  2020-07-08 17:48 ` [PATCH 1/8] dt-bindings: serial: renesas,scif: Document r8a774e1 bindings Lad Prabhakar
  2020-07-13 11:23   ` Geert Uytterhoeven
@ 2020-07-20 22:20   ` Rob Herring
  1 sibling, 0 replies; 25+ messages in thread
From: Rob Herring @ 2020-07-20 22:20 UTC (permalink / raw)
  To: Lad Prabhakar
  Cc: linux-kernel, linux-serial, linux-mmc, linux-arm-kernel,
	Thomas Gleixner, Rob Herring, Ulf Hansson, Greg Kroah-Hartman,
	Catalin Marinas, linux-renesas-soc, devicetree,
	Geert Uytterhoeven, Jason Cooper, Will Deacon, Prabhakar,
	Marc Zyngier, Magnus Damm

On Wed, 08 Jul 2020 18:48:24 +0100, Lad Prabhakar wrote:
> RZ/G2H (R8A774E1) SoC also has the R-Car gen3 compatible SCIF ports,
> so document the SoC specific bindings.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 2/8] dt-bindings: serial: renesas, hscif: Document r8a774e1 bindings
  2020-07-08 17:48 ` [PATCH 2/8] dt-bindings: serial: renesas,hscif: " Lad Prabhakar
  2020-07-13 11:24   ` Geert Uytterhoeven
@ 2020-07-20 22:20   ` Rob Herring
  1 sibling, 0 replies; 25+ messages in thread
From: Rob Herring @ 2020-07-20 22:20 UTC (permalink / raw)
  To: Lad Prabhakar
  Cc: Will Deacon, linux-kernel, linux-serial, Ulf Hansson,
	linux-arm-kernel, Thomas Gleixner, linux-mmc, devicetree,
	linux-renesas-soc, Rob Herring, Greg Kroah-Hartman, Marc Zyngier,
	Magnus Damm, Catalin Marinas, Geert Uytterhoeven, Jason Cooper,
	Prabhakar

On Wed, 08 Jul 2020 18:48:25 +0100, Lad Prabhakar wrote:
> RZ/G2H (R8A774E1) SoC also has the R-Car gen3 compatible HSCIF ports,
> so document the SoC specific bindings.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/serial/renesas,hscif.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 3/8] dt-bindings: irqchip: renesas-irqc: Document r8a774e1 bindings
  2020-07-08 17:48 ` [PATCH 3/8] dt-bindings: irqchip: renesas-irqc: " Lad Prabhakar
  2020-07-13 11:25   ` Geert Uytterhoeven
@ 2020-07-20 22:21   ` Rob Herring
  1 sibling, 0 replies; 25+ messages in thread
From: Rob Herring @ 2020-07-20 22:21 UTC (permalink / raw)
  To: Lad Prabhakar
  Cc: Geert Uytterhoeven, Thomas Gleixner, devicetree, Rob Herring,
	linux-arm-kernel, Marc Zyngier, Ulf Hansson, Catalin Marinas,
	Prabhakar, linux-serial, Greg Kroah-Hartman, linux-mmc,
	Will Deacon, linux-kernel, linux-renesas-soc, Magnus Damm,
	Jason Cooper

On Wed, 08 Jul 2020 18:48:26 +0100, Lad Prabhakar wrote:
> From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> 
> Document SoC specific bindings for RZ/G2H (r8a774e1) SoC.
> 
> Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  .../devicetree/bindings/interrupt-controller/renesas,irqc.yaml   | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 4/8] dt-bindings: mmc: renesas,sdhi: Add r8a774e1 support
  2020-07-08 17:48 ` [PATCH 4/8] dt-bindings: mmc: renesas,sdhi: Add r8a774e1 support Lad Prabhakar
  2020-07-13 11:26   ` Geert Uytterhoeven
@ 2020-07-20 22:21   ` Rob Herring
  1 sibling, 0 replies; 25+ messages in thread
From: Rob Herring @ 2020-07-20 22:21 UTC (permalink / raw)
  To: Lad Prabhakar
  Cc: Catalin Marinas, devicetree, Jason Cooper, Thomas Gleixner,
	linux-renesas-soc, Magnus Damm, linux-mmc, linux-kernel,
	Greg Kroah-Hartman, linux-arm-kernel, Prabhakar, linux-serial,
	Geert Uytterhoeven, Ulf Hansson, Marc Zyngier, Will Deacon,
	Rob Herring

On Wed, 08 Jul 2020 18:48:27 +0100, Lad Prabhakar wrote:
> Document SDHI controller for RZ/G2H (R8A774E1) SoC, which is compatible
> with R-Car Gen3 SoC family.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/mmc/renesas,sdhi.txt | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 25+ messages in thread

end of thread, back to index

Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-08 17:48 [PATCH 0/8] Add basic DT support for R8A774E1 SoC enabling HiHope RZ/G2H board Lad Prabhakar
2020-07-08 17:48 ` [PATCH 1/8] dt-bindings: serial: renesas,scif: Document r8a774e1 bindings Lad Prabhakar
2020-07-13 11:23   ` Geert Uytterhoeven
2020-07-20 22:20   ` [PATCH 1/8] dt-bindings: serial: renesas, scif: " Rob Herring
2020-07-08 17:48 ` [PATCH 2/8] dt-bindings: serial: renesas,hscif: " Lad Prabhakar
2020-07-13 11:24   ` Geert Uytterhoeven
2020-07-20 22:20   ` [PATCH 2/8] dt-bindings: serial: renesas, hscif: " Rob Herring
2020-07-08 17:48 ` [PATCH 3/8] dt-bindings: irqchip: renesas-irqc: " Lad Prabhakar
2020-07-13 11:25   ` Geert Uytterhoeven
2020-07-20 22:21   ` Rob Herring
2020-07-08 17:48 ` [PATCH 4/8] dt-bindings: mmc: renesas,sdhi: Add r8a774e1 support Lad Prabhakar
2020-07-13 11:26   ` Geert Uytterhoeven
2020-07-20 22:21   ` Rob Herring
2020-07-08 17:48 ` [PATCH 5/8] arm64: defconfig: Enable R8A774E1 SoC Lad Prabhakar
2020-07-13 11:28   ` Geert Uytterhoeven
2020-07-08 17:48 ` [PATCH 6/8] arm64: dts: renesas: Initial r8a774e1 SoC device tree Lad Prabhakar
2020-07-08 17:53   ` Marc Zyngier
2020-07-08 18:07     ` Lad, Prabhakar
2020-07-13 12:24   ` Geert Uytterhoeven
2020-07-16 14:50   ` Geert Uytterhoeven
2020-07-16 16:50     ` Prabhakar Mahadev Lad
2020-07-08 17:48 ` [PATCH 7/8] arm64: dts: renesas: Add HiHope RZ/G2H main board support Lad Prabhakar
2020-07-13 12:25   ` Geert Uytterhoeven
2020-07-08 17:48 ` [PATCH 8/8] arm64: dts: renesas: Add HiHope RZ/G2H sub " Lad Prabhakar
2020-07-13 12:25   ` Geert Uytterhoeven

Linux-Serial Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-serial/0 linux-serial/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-serial linux-serial/ https://lore.kernel.org/linux-serial \
		linux-serial@vger.kernel.org
	public-inbox-index linux-serial

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-serial


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git