From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 720BBC4320A for ; Sat, 21 Aug 2021 20:04:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 47CCE61245 for ; Sat, 21 Aug 2021 20:04:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230196AbhHUUFI (ORCPT ); Sat, 21 Aug 2021 16:05:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230206AbhHUUFH (ORCPT ); Sat, 21 Aug 2021 16:05:07 -0400 Received: from mail-vs1-xe36.google.com (mail-vs1-xe36.google.com [IPv6:2607:f8b0:4864:20::e36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B0BDC061760 for ; Sat, 21 Aug 2021 13:04:27 -0700 (PDT) Received: by mail-vs1-xe36.google.com with SMTP id h29so6124785vsr.7 for ; Sat, 21 Aug 2021 13:04:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=G38jY1tilTGN6yDwHsom5S6bcpGnsNsFIqj6vHXaM+4=; b=jbszNntP7qTNXuYqeSDrSwyTEJRUxrFw9Tszq2ShHFrKt+c5lI5tR1iD4bTU5W0CY6 +CIRYtl6wu5OzPTlhRq4xVu2fyRkkCshIJnzMGm8Uz+VgmoICIPSkqID4iLESFOzwJzO FfI3xg/pnuBnsa9QCjryMzEjzqIcvpU6cCqRUJkED4JBHaNQ8h3pmRDbtXD3XiLZP+sY D2kiu9zD3NZ04mNunkmIyGotJoS9joa0JNQy4rYj2iUaQiyJvG6w4rW+k55A6NaoBE1e qVnAgI0ULUX2/mmEHX0WIhzB6wxlAeydUSx6CNxYtUtb+CSqUsxo2EEA8huQ9kk+eTvO usRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=G38jY1tilTGN6yDwHsom5S6bcpGnsNsFIqj6vHXaM+4=; b=XRYmDPqXa5s/geZFJYGcjDnSDYvox/QckxxhMjryqOcUyqiLrbGR/T9bVtImWwjFDD rYMtmYyJZL215UWUj9lvVskriAZudg/cYczHBZO181CVdm9K+k59XDFmUAoDAH8/TtJr QUsWx8xgSGc5Q5JqGjfmW0fIsDKEsrI+8cUj9Ps5YJ7HaDMDUa7d7/Ce6r1x02qovKDn Gae9Tx+S3VNx4Y152HKprjiCHv45nv5KlmnBu296g5vjTFKIta3x34wkNRVk7/H8bvMp P+ni/hcKabZ0L8yMtxtAETJT2OEvPh7kwurRUmsmgD6AvxCE+ozgbHSdr6X3/K/v2MHz aMDA== X-Gm-Message-State: AOAM53304WMY2ZWi5G6GUeW4I8mXOPkRRbxh6u5Iu3jZlRvB2lKBk+zL 0f1sT4GrUk1wz/69mioazxza/1fJXW6Pay2CqzOYkw== X-Google-Smtp-Source: ABdhPJzU7hnomubaSHIzPBGsiWg0WU5H7lkMGJVnVU/4N1qnPmwHy/BZu/KqOcfxg7pCte4q8mzlxNLvP7gLbwusFfw= X-Received: by 2002:a67:16c1:: with SMTP id 184mr20698442vsw.14.1629576266521; Sat, 21 Aug 2021 13:04:26 -0700 (PDT) MIME-Version: 1.0 References: <20210811114827.27322-1-semen.protsenko@linaro.org> <20210811114827.27322-8-semen.protsenko@linaro.org> In-Reply-To: From: Sam Protsenko Date: Sat, 21 Aug 2021 23:04:14 +0300 Message-ID: Subject: Re: [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support To: Rob Herring Cc: Krzysztof Kozlowski , Sylwester Nawrocki , =?UTF-8?Q?Pawe=C5=82_Chmiel?= , Chanwoo Choi , Linus Walleij , Tomasz Figa , Marc Zyngier , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree , linux-arm Mailing List , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Linux Samsung SOC , "open list:SERIAL DRIVERS" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org On Tue, 17 Aug 2021 at 21:42, Rob Herring wrote: > > On Wed, Aug 11, 2021 at 02:48:27PM +0300, Sam Protsenko wrote: > > Samsung Exynos850 is ARMv8-based mobile-oriented SoC. > > > > This patch adds minimal SoC support by including next Device Tree nodes: > > > > 1. Octa cores (Cortex-A55), supporting PSCI v1.0 > > 2. ARM architecture timer (armv8-timer) > > 3. Interrupt controller (GIC-400) > > 4. Pinctrl nodes for GPIO > > 5. Serial node > > > > Signed-off-by: Sam Protsenko > > --- > > Changes in v3: > > - Used generic fixed clock for serial > > > > Changes in v2: > > * Commit message: > > - Documented added dts features instead of CPU features > > > > * exynos850-usi.dtsi: > > - Removed, moved everything to exynos850.dtsi > > > > * exynos850.dtsi: > > - Root node: > > - Added comment about engineering name (Exynos3830) > > - Renamed pinctrl nodes, adding domain names > > - Used hard coded IRQ numbers instead of named constants everywhere > > - Added soc node, moved next nodes there: gic, clock, pinctrls and > > serial > > - Used address-cells=1 for soc node and removed unneeded 0x0 from > > reg properties > > - Moved exynos850-pinctrl.dtsi include line to the end of > > exynos850.dtsi > > - Coding style fixes > > - cpus: > > - Used address-cells=1 for cpus node > > - Renamed cpu@0001 to cpu@1, and so on > > - Left only "arm,cortex-a55" for cpus compatible > > - Renamed reg = <0x0001> to <0x1> for cpus > > - armv8 timer: > > - Add comment about missing HV timer IRQ to armv8 timer node > > - Removed not existing properties from armv8 timer node > > - Fixed cpu number in CPU_MASK() > > - Removed obsolete clock-frequency property > > - GIC: > > - Fixed GIC type to be GIC-400 > > - Fixed size of GIC's 2nd region to be 0x2000 > > - serial node: > > - Hard coded clock number for serial_0 for now; will replace with > > named const once proper clock driver is implemented > > - Removed gate_uart_clk0 clock from serial_0, as that clock is not > > supported in serial driver anyway (yet) > > - clock node: > > - Fixed clock controller node name (@0x12.. -> @12..) > > > > * exynos850-pinctrl.dtsi: > > - Referenced pinctrl nodes instead of defining those again in root node > > - Fixed interrupt-cells (3 -> 2) > > - Fixed USI related comments for pin config nodes > > - Removed decon_f_te_* and fm_lna_en nodes (won't be used) > > - Reordered pin config nodes by pin numbers > > - Improved all comments > > - Used existing named constants for pin-function and pin-pud > > - Fixed node names (used hyphens instead of underscore) > > - Fixed warnings found in W=1 build > > > > .../boot/dts/exynos/exynos850-pinctrl.dtsi | 748 ++++++++++++++++++ > > arch/arm64/boot/dts/exynos/exynos850.dtsi | 261 ++++++ > > 2 files changed, 1009 insertions(+) > > create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi > > create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi > > > > diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi > > new file mode 100644 > > index 000000000000..ba5d5f33e2f6 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi > > @@ -0,0 +1,748 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source > > + * > > + * Copyright (C) 2017 Samsung Electronics Co., Ltd. > > + * Copyright (C) 2021 Linaro Ltd. > > + * > > + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device > > + * tree nodes in this file. > > + */ > > + > > +#include > > +#include > > + > > +&pinctrl_alive { > > + gpa0: gpa0 { > > + gpio-controller; > > + #gpio-cells = <2>; > > + > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + interrupt-parent = <&gic>; > > + interrupts = , > > + , > > + , > > + , > > + , > > + , > > + , > > + ; > > + }; > > + > > + gpa1: gpa1 { > > + gpio-controller; > > + #gpio-cells = <2>; > > + > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + interrupt-parent = <&gic>; > > + interrupts = , > > + , > > + , > > + , > > + , > > + , > > + , > > + ; > > + }; > > + > > + gpa2: gpa2 { > > + gpio-controller; > > + #gpio-cells = <2>; > > + > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + interrupt-parent = <&gic>; > > + interrupts = , > > + , > > + , > > + , > > + , > > + , > > + , > > + ; > > + }; > > + > > + gpa3: gpa3 { > > + gpio-controller; > > + #gpio-cells = <2>; > > + > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + interrupt-parent = <&gic>; > > + interrupts = , > > + , > > + , > > + , > > + , > > + , > > + , > > + ; > > + }; > > + > > + gpa4: gpa4 { > > + gpio-controller; > > + #gpio-cells = <2>; > > + > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + interrupt-parent = <&gic>; > > + interrupts = , > > + , > > + , > > + ; > > + }; > > + > > + gpq0: gpq0 { > > + gpio-controller; > > + #gpio-cells = <2>; > > + > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + }; > > + > > + /* I2C5 (also called CAM_PMIC_I2C in TRM) */ > > + i2c5_bus: i2c5-bus { > > Please name all the pinctrl nodes with some pattern you can match on > once there is a schema. '-pins$' is my suggestion. > Done. This looks much better, the change will be present in new patch series including board dts. Can I ask for more info about schema you mentioned: is there some doc or examples I can check? And is it something generic, or I have to implement it for Exynos850 dts? Thanks! > > + samsung,pins = "gpa3-5", "gpa3-6"; > > + samsung,pin-function = ; > > + samsung,pin-pud = ; > > + samsung,pin-drv = <0>; > > + }; > > + > > + /* I2C6 (also called MOTOR_I2C in TRM) */ > > + i2c6_bus: i2c6-bus { > > + samsung,pins = "gpa3-7", "gpa4-0"; > > + samsung,pin-function = ; > > + samsung,pin-pud = ; > > + samsung,pin-drv = <0>; > > + };