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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Mateusz Holenko <mholenko@antmicro.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jiri Slaby <jslaby@suse.com>,
	devicetree@vger.kernel.org, linux-serial@vger.kernel.org
Cc: Stafford Horne <shorne@gmail.com>,
	Karol Gugala <kgugala@antmicro.com>,
	Mauro Carvalho Chehab <mchehab+samsung@kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	"Paul E. McKenney" <paulmck@linux.ibm.com>,
	Filip Kokosinski <fkokosinski@antmicro.com>,
	Pawel Czarnecki <pczarnecki@internships.antmicro.com>,
	Joel Stanley <joel@jms.id.au>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Maxime Ripard <mripard@kernel.org>,
	Shawn Guo <shawnguo@kernel.org>, Heiko Stuebner <heiko@sntech.de>,
	Sam Ravnborg <sam@ravnborg.org>, Icenowy Zheng <icenowy@aosc.io>,
	Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 3/5] drivers/soc/litex: add LiteX SoC Controller driver
Date: Wed, 29 Apr 2020 13:11:54 +1000	[thread overview]
Message-ID: <aa7c915310753b042be35758893dee91d3651ffc.camel@kernel.crashing.org> (raw)
In-Reply-To: <20200425133939.3508912-3-mholenko@antmicro.com>

On Sat, 2020-04-25 at 13:42 +0200, Mateusz Holenko wrote:
> From: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
> 
> This commit adds driver for the FPGA-based LiteX SoC
> Controller from LiteX SoC builder.

Sorry for jumping in late, Joel only just pointed me to this :)

> + * The purpose of `litex_set_reg`/`litex_get_reg` is to implement
> + * the logic of writing to/reading from the LiteX CSR in a single
> + * place that can be then reused by all LiteX drivers.
> + */
> +void litex_set_reg(void __iomem *reg, unsigned long reg_size,
> +		    unsigned long val)
> +{
> +	unsigned long shifted_data, shift, i;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&csr_lock, flags);
> +
> +	for (i = 0; i < reg_size; ++i) {
> +		shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT);
> +		shifted_data = val >> shift;
> +
> +		__raw_writel(shifted_data, reg + (LITEX_REG_SIZE * i));
> +	}
> +
> +	spin_unlock_irqrestore(&csr_lock, flags);
> +}
> +
> +unsigned long litex_get_reg(void __iomem *reg, unsigned long reg_size)
> +{
> +	unsigned long shifted_data, shift, i;
> +	unsigned long result = 0;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&csr_lock, flags);
> +
> +	for (i = 0; i < reg_size; ++i) {
> +		shifted_data = __raw_readl(reg + (LITEX_REG_SIZE * i));
> +
> +		shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT);
> +		result |= (shifted_data << shift);
> +	}
> +
> +	spin_unlock_irqrestore(&csr_lock, flags);
> +
> +	return result;
> +}

I really don't like the fact that the register sizes & sub sizes are
#defined. As your comment explains, this makes it harder to support
other configurations. This geometry should come from the device-tree
instead.

Also this while thing is rather gross (and the lock will not help
performance). Why can't CSRs be normally memory mapped always instead ?

Even when transporting them on a HW bus that's smaller, the HW bus
conversion should be able to do the break-down into a multi-breat
transfer rather than doing that in SW.

Or at least have a fast-path if the register size is no larger than the
sub size, so you can use a normal ioread32/iowrite32.

Also I wonder ... last I played with LiteX, it would re-generate the
register layout (including the bit layout inside registers potentially)
rather enthousiastically, making it pretty hard to have a fixed
register layout for use by a kernel driver. Was this addressed ?

Cheers,
Ben.



  parent reply	other threads:[~2020-04-29  3:31 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-25 11:41 [PATCH v5 0/5] LiteX SoC controller and LiteUART serial driver Mateusz Holenko
2020-04-25 11:41 ` [PATCH v5 1/5] dt-bindings: vendor: add vendor prefix for LiteX Mateusz Holenko
2020-04-25 11:41 ` [PATCH v5 2/5] dt-bindings: soc: document LiteX SoC Controller bindings Mateusz Holenko
2020-04-25 11:42 ` [PATCH v5 3/5] drivers/soc/litex: add LiteX SoC Controller driver Mateusz Holenko
2020-04-27  9:13   ` Mateusz Holenko
2020-04-29  3:21     ` Benjamin Herrenschmidt
2020-04-29 11:32       ` Gabriel L. Somlo
2020-04-29  3:11   ` Benjamin Herrenschmidt [this message]
2020-05-07  7:36     ` Mateusz Holenko
2020-04-25 11:42 ` [PATCH v5 4/5] dt-bindings: serial: document LiteUART bindings Mateusz Holenko
2020-04-25 11:42 ` [PATCH v5 5/5] drivers/tty/serial: add LiteUART driver Mateusz Holenko
2020-04-28 15:50   ` Andy Shevchenko
2020-05-04 13:44     ` Mateusz Holenko
2020-05-05 14:02       ` Andy Shevchenko
2020-05-08 10:16         ` Mateusz Holenko

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