[PATCH v4] serial: exar: Fix GPIO configuration for Sealevel cards based on XR17V35X

[Matthew Howell <mrhowel@g.clemson.edu>]

From: Matthew Howell <matthew.howell@sealevel.com>

Sealevel XR17V35X based devices are inoperable on kernel versions
4.11 and above due to a change in the GPIO preconfiguration introduced in
commit
7dea8165f1d. This patch fixes this by preconfiguring the GPIO on Sealevel
cards to the value (0x00) used prior to commit 7dea8165f1d

With GPIOs preconfigured as per commit 7dea8165f1d all ports on
Sealevel XR17V35X based devices become stuck in high impedance
mode, regardless of dip-switch or software configuration. This
causes the device to become effectively unusable. This patch (in
various forms) has been distributed to our customers and no issues
related to it have been reported.

Fixes: 7dea8165f1d ("serial: exar: Preconfigure xr17v35x MPIOs as output")
Signed-off-by: Matthew Howell <matthew.howell@sealevel.com>
---

Revised based on comments received on previous submission
https://www.spinics.net/lists/linux-serial/msg39482.html

It had previously passed checkpatch.pl in "patch" mode (--patch)
without errors. However, when running it in "file" mode (-f) it finds
stling issues that did not show up in "patch" mode. These styling
issues are now resolved according to checkpatch.pl. It appears my
editor (and email client) were automatically converting tabs
to spaces.

Let me know if the tabs are still being converted to spaces somehow
or if anything else looks wrong.

--- linux/drivers/tty/serial/8250/8250_exar.c.orig	2020-07-09 11:05:03.920060577 -0400
+++ linux/drivers/tty/serial/8250/8250_exar.c	2020-07-22 14:08:27.494512202 -0400
@@ -326,7 +326,17 @@ static void setup_gpio(struct pci_dev *p
 	 * devices will export them as GPIOs, so we pre-configure them safely
 	 * as inputs.
 	 */
-	u8 dir = pcidev->vendor == PCI_VENDOR_ID_EXAR ? 0xff : 0x00;
+
+	u8 dir = 0x00;
+
+	if  ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
+		(pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
+		// Configure GPIO as inputs for Commtech adapters
+		dir = 0xff;
+	} else {
+		// Configure GPIO as outputs for SeaLevel adapters
+		dir = 0x00;
+	}

 	writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
 	writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);