From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Mikulas Patocka <mpatocka@redhat.com>,
Richard Henderson <rth@twiddle.net>,
Ivan Kokshaysky <ink@jurassic.park.msu.ru>,
Matt Turner <mattst88@gmail.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
alpha <linux-alpha@vger.kernel.org>,
linux-serial@vger.kernel.org, linux-rtc@vger.kernel.org
Subject: Re: [PATCH v4] alpha: add a barrier after outb, outw and outl
Date: Sun, 10 May 2020 02:27:10 +0100 (BST) [thread overview]
Message-ID: <alpine.LFD.2.21.2005100153470.487915@eddie.linux-mips.org> (raw)
In-Reply-To: <CAK8P3a3SBg=w72KVgGUGAUcmU-6RxrQW=mnYf8vmFjBL5jbDpg@mail.gmail.com>
On Thu, 7 May 2020, Arnd Bergmann wrote:
> > The patch 92d7223a74235054f2aa7227d207d9c57f84dca0 ("alpha: io: reorder
> > barriers to guarantee writeX() and iowriteX() ordering #2") broke boot on
> > the Alpha Avanti platform.
> >
> > The patch changes timing between accesses to the ISA bus, in particular,
> > it reduces the time between "write" access and a subsequent "read" access.
> >
> > This causes lock-up when accessing the real time clock and serial ports.
> >
> > This patch fixes the bug by adding a memory barrier after the functions
> > that access the ISA ports - outb, outw, outl. The barrier causes that
> > there is some delay between the write to an IO port and a subsequent read.
There is no delay guarantee, just an in-order completion guarantee:
#define mb() __asm__ __volatile__("mb": : :"memory")
MB is a hardware memory barrier instruction.
> Based on your earlier explanations, I would mention here that the barrier
> avoids the back-to-back I/O instructions on the bus that seem to be causing
> the problem. As I understand it (having very little alpha specific knowledge),
> they should prevent them by design. However if you are sure it's just the
> added delay rather than any actual barrier effect, that would also be worth
> pointing out.
Alpha is weakly ordered, also WRT MMIO. Writing a simple test program to
poke directly (e.g. using `ioremap' and then inline asm on the location
obtained) at RTC and UART registers would be a good way to determine what
is really going on here.
Maciej
next prev parent reply other threads:[~2020-05-13 22:46 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-06 11:21 [PATCH 1/2] alpha: add a delay between RTC port write and read Mikulas Patocka
2020-05-06 14:20 ` Arnd Bergmann
2020-05-06 17:12 ` [PATCH 1/2 v2] alpha: add a delay to inb_p, inb_w and inb_l Mikulas Patocka
2020-05-07 8:06 ` [PATCH 1/2 v3] " Mikulas Patocka
2020-05-07 8:20 ` Greg Kroah-Hartman
2020-05-07 10:53 ` Mikulas Patocka
2020-05-07 13:30 ` Arnd Bergmann
2020-05-07 14:09 ` Mikulas Patocka
2020-05-07 15:08 ` Arnd Bergmann
2020-05-07 15:45 ` Mikulas Patocka
2020-05-07 15:46 ` [PATCH v4] alpha: add a barrier after outb, outw and outl Mikulas Patocka
2020-05-07 19:12 ` Arnd Bergmann
2020-05-10 1:27 ` Maciej W. Rozycki [this message]
2020-05-10 1:25 ` [PATCH 1/2 v3] alpha: add a delay to inb_p, inb_w and inb_l Maciej W. Rozycki
2020-05-10 18:50 ` Mikulas Patocka
2020-05-11 14:58 ` Maciej W. Rozycki
2020-05-12 19:35 ` Mikulas Patocka
2020-05-13 14:41 ` Ivan Kokshaysky
2020-05-13 16:13 ` Greg Kroah-Hartman
2020-05-13 17:17 ` Maciej W. Rozycki
2020-05-22 13:03 ` Mikulas Patocka
2020-05-22 13:37 ` Maciej W. Rozycki
2020-05-22 13:26 ` Mikulas Patocka
2020-05-22 20:00 ` Mikulas Patocka
2020-05-23 10:26 ` [PATCH v4] alpha: fix memory barriers so that they conform to the specification Mikulas Patocka
2020-05-23 15:10 ` Ivan Kokshaysky
2020-05-23 15:34 ` Mikulas Patocka
2020-05-23 15:37 ` [PATCH v5] " Mikulas Patocka
2020-05-24 14:54 ` Maciej W. Rozycki
2020-05-25 13:56 ` Mikulas Patocka
2020-05-25 14:07 ` Arnd Bergmann
2020-05-25 14:45 ` Maciej W. Rozycki
2020-05-25 15:53 ` [PATCH v6] " Mikulas Patocka
2020-05-26 14:47 ` [PATCH v7] " Mikulas Patocka
2020-05-27 0:18 ` Maciej W. Rozycki
2020-06-08 6:58 ` Mikulas Patocka
2020-06-08 23:49 ` Matt Turner
2020-05-25 15:54 ` [PATCH v5] " Mikulas Patocka
2020-05-25 16:39 ` Maciej W. Rozycki
2020-05-26 14:48 ` Mikulas Patocka
2020-05-27 0:23 ` Maciej W. Rozycki
2020-05-23 16:44 ` [PATCH v4] " Maciej W. Rozycki
2020-05-23 17:09 ` Mikulas Patocka
2020-05-23 19:27 ` Maciej W. Rozycki
2020-05-23 20:11 ` Mikulas Patocka
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