* [PATCH 0/4] Add basic node support for Mediatek MT8192 SoC
@ 2020-07-23 9:07 Seiya Wang
2020-07-23 9:07 ` [PATCH 1/4] arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile Seiya Wang
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Seiya Wang @ 2020-07-23 9:07 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Matthias Brugger,
Wim Van Sebroeck, Guenter Roeck
Cc: linux-serial, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, linux-watchdog, srv_heupstream
MT8192 is a SoC based on 64bit ARMv8 architecture.
It contains 4 CA55 and 4 CA76 cores.
MT8192 share many HW IP with MT65xx series.
This patchset was tested on MT8192 evaluation board and use correct clock to she
ll.
Based on v5.8-rc1
Crystal Guo (2):
watchdog: mt8192: add wdt support
dt-binding: mediatek: mt8192: update mtk-wdt document
Seiya Wang (2):
arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and
Makefile
dt-bindings: serial: Add compatible for Mediatek MT8192
---
This patch depends on
[PATCH 1/3] dt-bindings: pinctrl: mt8192: add pinctrl file
[PATCH 2/3] dt-bindings: pinctrl: mt8192: add binding document
[PATCH v2 3/4] dt-bindings: mediatek: add compatible for MT6873/8192 pwrap
[PATCH v2 1/2] dt-bindings: spi: update bindings for MT8192 SoC
[PATCH 2/4] clk: mediatek: Add dt-bindings for MT8192 clocks
[PATCH 1/4] dt-bindings: ARM: Mediatek: Document bindings for MT8192
Please also accept this patch together with [1][2][3][4][5][6]
to avoid build and dt binding check error.
[1] http://lists.infradead.org/pipermail/linux-mediatek/2020-July/014042.html
[2] http://lists.infradead.org/pipermail/linux-mediatek/2020-July/014043.html
[3] http://lists.infradead.org/pipermail/linux-mediatek/2020-July/014546.html
[4] http://lists.infradead.org/pipermail/linux-mediatek/2020-July/014406.html
[5] http://lists.infradead.org/pipermail/linux-mediatek/2020-July/014450.html
[6] http://lists.infradead.org/pipermail/linux-mediatek/2020-July/014451.html
---
.../devicetree/bindings/serial/mtk-uart.txt | 1 +
.../devicetree/bindings/watchdog/mtk-wdt.txt | 2 +
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 29 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 663 +++++++++++++++++++++
drivers/watchdog/mtk_wdt.c | 5 +
6 files changed, 701 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8192.dtsi
--
2.14.1
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 1/4] arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile 2020-07-23 9:07 [PATCH 0/4] Add basic node support for Mediatek MT8192 SoC Seiya Wang @ 2020-07-23 9:07 ` Seiya Wang 2020-07-23 9:07 ` [PATCH 2/4] dt-bindings: serial: Add compatible for Mediatek MT8192 Seiya Wang ` (2 subsequent siblings) 3 siblings, 0 replies; 11+ messages in thread From: Seiya Wang @ 2020-07-23 9:07 UTC (permalink / raw) To: Greg Kroah-Hartman, Rob Herring, Matthias Brugger, Wim Van Sebroeck, Guenter Roeck Cc: linux-serial, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-watchdog, srv_heupstream, Seiya Wang Add basic chip support for Mediatek MT8192, include uart, watchdog, spi, pinctrl, pwrap and clock controller nodes. Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 29 ++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 663 ++++++++++++++++++++++++++++ 3 files changed, 693 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8192.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index a57af9da9f5c..80320ed2d82c 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -11,4 +11,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts new file mode 100644 index 000000000000..0205837fa698 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 MediaTek Inc. + * Author: Seiya Wang <seiya.wang@mediatek.com> + */ +/dts-v1/; +#include "mt8192.dtsi" + +/ { + model = "MediaTek MT8192 evaluation board"; + compatible = "mediatek,mt8192-evb", "mediatek,mt8192"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi new file mode 100644 index 000000000000..7d724f24fc9e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -0,0 +1,663 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 MediaTek Inc. + * Author: Seiya Wang <seiya.wang@mediatek.com> + */ + +/dts-v1/; +#include <dt-bindings/clock/mt8192-clk.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/mt8192-pinfunc.h> +#include <dt-bindings/power/mt8192-power.h> + +/ { + compatible = "mediatek,mt8192"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clk26m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x000>; + enable-method = "psci"; + clock-frequency = <1701000000>; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <768>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + clock-frequency = <1701000000>; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <768>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + clock-frequency = <1701000000>; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <768>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + clock-frequency = <1701000000>; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <768>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x400>; + enable-method = "psci"; + clock-frequency = <2171000000>; + next-level-cache = <&l2_1>; + capacity-dmips-mhz = <1024>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x500>; + enable-method = "psci"; + clock-frequency = <2171000000>; + next-level-cache = <&l2_1>; + capacity-dmips-mhz = <1024>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + clock-frequency = <2171000000>; + next-level-cache = <&l2_1>; + capacity-dmips-mhz = <1024>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + clock-frequency = <2171000000>; + next-level-cache = <&l2_1>; + capacity-dmips-mhz = <1024>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l3_0: l3-cache { + compatible = "cache"; + }; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; + clock-frequency = <13000000>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + #redistributor-regions = <1>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + }; + + topckgen: topckgen@10000000 { + compatible = "mediatek,mt8192-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt8192-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg: pericfg@10003000 { + compatible = "mediatek,mt8192-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8192-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c20000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", + "iocfg_bl", "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + }; + + scpsys: power-controller@10006000 { + compatible = "mediatek,mt8192-scpsys", "syscon"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>, + <&topckgen CLK_TOP_IMG1_SEL>, + <&topckgen CLK_TOP_IMG2_SEL>, + <&topckgen CLK_TOP_IPE_SEL>, + <&topckgen CLK_TOP_VDEC_SEL>, + <&topckgen CLK_TOP_VENC_SEL>, + <&topckgen CLK_TOP_MDP_SEL>, + <&topckgen CLK_TOP_DISP_SEL>, + <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&infracfg CLK_INFRA_AUDIO_26M_B>, + <&infracfg CLK_INFRA_AUDIO>, + <&topckgen CLK_TOP_ADSP_SEL>, + <&topckgen CLK_TOP_CAM_SEL>, + <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>, + <&imgsys2 CLK_IMG2_LARB11>, + <&imgsys2 CLK_IMG2_GALS>, + <&ipesys CLK_IPE_LARB19>, + <&ipesys CLK_IPE_LARB20>, + <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_GALS>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>, + <&vencsys CLK_VENC_SET1_VENC>, + <&mdpsys CLK_MDP_SMI0>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_IOMMU>, + <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_CCU_GALS>, + <&camsys CLK_CAM_CAM2MM_GALS>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>, + <&camsys_rawb CLK_CAM_RAWB_LARBX>, + <&camsys_rawc CLK_CAM_RAWC_LARBX>; + clock-names = "mfg", "isp", "isp2", "ipe", "vdec", + "venc", "mdp", "disp", "audio", "audio1", + "audio2", "adsp", "cam", "isp-0", + "isp-1", "isp2-0", "isp2-1", "ipe-0", + "ipe-1", "ipe-2", "ipe-3", "vdec-0", + "vdec-1", "vdec-2", "vdec2-0", "vdec2-1", + "vdec2-2", "venc-0", "mdp-0", "disp-0", + "disp-1", "disp-2", "disp-3", "cam-0", + "cam-1", "cam-2", "cam-3", "cam_rawa-0", + "cam_rawb-0", "cam_rawc-0"; + infracfg = <&infracfg>; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8192-wdt"; + reg = <0 0x10007000 0 0x100>; + #reset-cells = <1>; + }; + + apmixedsys: apmixedsys@1000c000 { + compatible = "mediatek,mt8192-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + pwrap: pwrap@10026000 { + compatible = "mediatek,mt6873-pwrap"; + reg = <0 0x10026000 0 0x1000>; + reg-names = "pwrap"; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>; + clock-names = "spi", "wrap"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; + + spmi_bus: spmi@10027000 { + compatible = "mediatek,pmif"; + reg = <0 0x10027000 0 0x000e00>, + <0 0x10027f00 0 0x00008c>, + <0 0x10029000 0 0x000100>; + reg-names = "pmif", "pmifmpu", "spmimst"; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "pmif_irq"; + irq_event_en = <0x0 0x0 0x00300000 0x00000100 0x0>; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST_SEL>; + clock-names = "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + swinf_ch_start = <4>; + ap_swinf_no = <2>; + }; + + scp_adsp: scp_adsp@10720000 { + compatible = "mediatek,mt8192-scp_adsp", "syscon"; + reg = <0 0x10720000 0 0x1000>; + #clock-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8192-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8192-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + imp_iic_wrap_c: imp_iic_wrap_c@11007000 { + compatible = "mediatek,mt8192-imp_iic_wrap_c", "syscon"; + reg = <0 0x11007000 0 0x1000>; + #clock-cells = <1>; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi1: spi@11010000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11010000 0 0x1000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11012000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11012000 0 0x1000>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11013000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11013000 0 0x1000>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi4: spi@11018000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11018000 0 0x1000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI4>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11019000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11019000 0 0x1000>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi6: spi@1101d000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1101d000 0 0x1000>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI6>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi7: spi@1101e000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1101e000 0 0x1000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI7>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + audsys: audsys@11210000 { + compatible = "mediatek,mt8192-audsys", "syscon"; + reg = <0 0x11210000 0 0x1000>; + #clock-cells = <1>; + }; + + imp_iic_wrap_e: imp_iic_wrap_e@11cb1000 { + compatible = "mediatek,mt8192-imp_iic_wrap_e", "syscon"; + reg = <0 0x11cb1000 0 0x1000>; + #clock-cells = <1>; + }; + + imp_iic_wrap_s: imp_iic_wrap_s@11d03000 { + compatible = "mediatek,mt8192-imp_iic_wrap_s", "syscon"; + reg = <0 0x11d03000 0 0x1000>; + #clock-cells = <1>; + }; + + imp_iic_wrap_ws: imp_iic_wrap_ws@11d23000 { + compatible = "mediatek,mt8192-imp_iic_wrap_ws", "syscon"; + reg = <0 0x11d23000 0 0x1000>; + #clock-cells = <1>; + }; + + imp_iic_wrap_w: imp_iic_wrap_w@11e01000 { + compatible = "mediatek,mt8192-imp_iic_wrap_w", "syscon"; + reg = <0 0x11e01000 0 0x1000>; + #clock-cells = <1>; + }; + + imp_iic_wrap_n: imp_iic_wrap_n@11f02000 { + compatible = "mediatek,mt8192-imp_iic_wrap_n", "syscon"; + reg = <0 0x11f02000 0 0x1000>; + #clock-cells = <1>; + }; + + msdc_top: msdc_top@11f10000 { + compatible = "mediatek,mt8192-msdc_top", "syscon"; + reg = <0 0x11f10000 0 0x1000>; + #clock-cells = <1>; + }; + + msdc: msdc@11f60000 { + compatible = "mediatek,mt8192-msdc", "syscon"; + reg = <0 0x11f60000 0 0x1000>; + #clock-cells = <1>; + }; + + mfgcfg: mfgcfg@13fbf000 { + compatible = "mediatek,mt8192-mfgcfg", "syscon"; + reg = <0 0x13fbf000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: mmsys@14000000 { + compatible = "mediatek,mt8192-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: imgsys@15020000 { + compatible = "mediatek,mt8192-imgsys", "syscon"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys2: imgsys2@15820000 { + compatible = "mediatek,mt8192-imgsys2", "syscon"; + reg = <0 0x15820000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys_soc: vdecsys_soc@1600f000 { + compatible = "mediatek,mt8192-vdecsys_soc", "syscon"; + reg = <0 0x1600f000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: vdecsys@1602f000 { + compatible = "mediatek,mt8192-vdecsys", "syscon"; + reg = <0 0x1602f000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: vencsys@17000000 { + compatible = "mediatek,mt8192-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + apu_conn: apu_conn@19020000 { + compatible = "mediatek,mt8192-apu_conn", "syscon"; + reg = <0 0x19020000 0 0x1000>; + #clock-cells = <1>; + }; + + apu_vcore: apu_vcore@19029000 { + compatible = "mediatek,mt8192-apu_vcore", "syscon"; + reg = <0 0x19029000 0 0x1000>; + #clock-cells = <1>; + }; + + apu0: apu0@19030000 { + compatible = "mediatek,mt8192-apu0", "syscon"; + reg = <0 0x19030000 0 0x1000>; + #clock-cells = <1>; + }; + + apu1: apu1@19031000 { + compatible = "mediatek,mt8192-apu1", "syscon"; + reg = <0 0x19031000 0 0x1000>; + #clock-cells = <1>; + }; + + apu_mdla0: apu_mdla0@19034000 { + compatible = "mediatek,mt8192-apu_mdla0", "syscon"; + reg = <0 0x19034000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: camsys@1a000000 { + compatible = "mediatek,mt8192-camsys", "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawa: camsys_rawa@1a04f000 { + compatible = "mediatek,mt8192-camsys_rawa", "syscon"; + reg = <0 0x1a04f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawb: camsys_rawb@1a06f000 { + compatible = "mediatek,mt8192-camsys_rawb", "syscon"; + reg = <0 0x1a06f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawc: camsys_rawc@1a08f000 { + compatible = "mediatek,mt8192-camsys_rawc", "syscon"; + reg = <0 0x1a08f000 0 0x1000>; + #clock-cells = <1>; + }; + + ipesys: ipesys@1b000000 { + compatible = "mediatek,mt8192-ipesys", "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + mdpsys: mdpsys@1f000000 { + compatible = "mediatek,mt8192-mdpsys", "syscon"; + reg = <0 0x1f000000 0 0x1000>; + #clock-cells = <1>; + }; + }; +}; -- 2.14.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/4] dt-bindings: serial: Add compatible for Mediatek MT8192 2020-07-23 9:07 [PATCH 0/4] Add basic node support for Mediatek MT8192 SoC Seiya Wang 2020-07-23 9:07 ` [PATCH 1/4] arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile Seiya Wang @ 2020-07-23 9:07 ` Seiya Wang 2020-07-23 21:28 ` Rob Herring 2020-07-23 9:07 ` [PATCH 3/4] watchdog: mt8192: add wdt support Seiya Wang 2020-07-23 9:07 ` [PATCH 4/4] dt-binding: mediatek: mt8192: update mtk-wdt document Seiya Wang 3 siblings, 1 reply; 11+ messages in thread From: Seiya Wang @ 2020-07-23 9:07 UTC (permalink / raw) To: Greg Kroah-Hartman, Rob Herring, Matthias Brugger, Wim Van Sebroeck, Guenter Roeck Cc: linux-serial, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-watchdog, srv_heupstream, Seiya Wang This commit adds dt-binding documentation of uart for Mediatek MT8192 SoC Platform. Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> --- Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt index 3a3b57079f0d..647b5aee86f3 100644 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt @@ -19,6 +19,7 @@ Required properties: * "mediatek,mt8135-uart" for MT8135 compatible UARTS * "mediatek,mt8173-uart" for MT8173 compatible UARTS * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS + * "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS * "mediatek,mt8516-uart" for MT8516 compatible UARTS * "mediatek,mt6577-uart" for MT6577 and all of the above -- 2.14.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 2/4] dt-bindings: serial: Add compatible for Mediatek MT8192 2020-07-23 9:07 ` [PATCH 2/4] dt-bindings: serial: Add compatible for Mediatek MT8192 Seiya Wang @ 2020-07-23 21:28 ` Rob Herring 0 siblings, 0 replies; 11+ messages in thread From: Rob Herring @ 2020-07-23 21:28 UTC (permalink / raw) To: Seiya Wang Cc: linux-mediatek, Matthias Brugger, devicetree, Greg Kroah-Hartman, Rob Herring, linux-arm-kernel, srv_heupstream, linux-kernel, Wim Van Sebroeck, linux-watchdog, Guenter Roeck, linux-serial On Thu, 23 Jul 2020 17:07:29 +0800, Seiya Wang wrote: > This commit adds dt-binding documentation of uart for Mediatek MT8192 SoC > Platform. > > Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> > --- > Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/4] watchdog: mt8192: add wdt support 2020-07-23 9:07 [PATCH 0/4] Add basic node support for Mediatek MT8192 SoC Seiya Wang 2020-07-23 9:07 ` [PATCH 1/4] arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile Seiya Wang 2020-07-23 9:07 ` [PATCH 2/4] dt-bindings: serial: Add compatible for Mediatek MT8192 Seiya Wang @ 2020-07-23 9:07 ` Seiya Wang 2020-07-23 22:00 ` Matthias Brugger 2020-07-23 9:07 ` [PATCH 4/4] dt-binding: mediatek: mt8192: update mtk-wdt document Seiya Wang 3 siblings, 1 reply; 11+ messages in thread From: Seiya Wang @ 2020-07-23 9:07 UTC (permalink / raw) To: Greg Kroah-Hartman, Rob Herring, Matthias Brugger, Wim Van Sebroeck, Guenter Roeck Cc: linux-serial, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-watchdog, srv_heupstream, Crystal Guo From: Crystal Guo <crystal.guo@mediatek.com> add driver setting to support mt8192 wdt Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> --- drivers/watchdog/mtk_wdt.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index d6a6393f609d..ad23596170af 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -76,6 +76,10 @@ static const struct mtk_wdt_data mt8183_data = { .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, }; +static const struct mtk_wdt_data mt8192_data = { + .toprgu_sw_rst_num = 23, +}; + static int toprgu_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -322,6 +326,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = { { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, { .compatible = "mediatek,mt6589-wdt" }, { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, + { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); -- 2.14.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 3/4] watchdog: mt8192: add wdt support 2020-07-23 9:07 ` [PATCH 3/4] watchdog: mt8192: add wdt support Seiya Wang @ 2020-07-23 22:00 ` Matthias Brugger 2020-07-24 7:02 ` Crystal Guo 0 siblings, 1 reply; 11+ messages in thread From: Matthias Brugger @ 2020-07-23 22:00 UTC (permalink / raw) To: Seiya Wang, Greg Kroah-Hartman, Rob Herring, Wim Van Sebroeck, Guenter Roeck Cc: linux-serial, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-watchdog, srv_heupstream, Crystal Guo On 23/07/2020 11:07, Seiya Wang wrote: > From: Crystal Guo <crystal.guo@mediatek.com> > > add driver setting to support mt8192 wdt > > Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> > --- > drivers/watchdog/mtk_wdt.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c > index d6a6393f609d..ad23596170af 100644 > --- a/drivers/watchdog/mtk_wdt.c > +++ b/drivers/watchdog/mtk_wdt.c > @@ -76,6 +76,10 @@ static const struct mtk_wdt_data mt8183_data = { > .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, > }; > > +static const struct mtk_wdt_data mt8192_data = { > + .toprgu_sw_rst_num = 23, Should be defined in include/dt-bindings/reset-controller/mt8192-resets.h > +}; > + > static int toprgu_reset_update(struct reset_controller_dev *rcdev, > unsigned long id, bool assert) > { > @@ -322,6 +326,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = { > { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, > { .compatible = "mediatek,mt6589-wdt" }, > { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, > + { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, > { /* sentinel */ } > }; > MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/4] watchdog: mt8192: add wdt support 2020-07-23 22:00 ` Matthias Brugger @ 2020-07-24 7:02 ` Crystal Guo 0 siblings, 0 replies; 11+ messages in thread From: Crystal Guo @ 2020-07-24 7:02 UTC (permalink / raw) To: Matthias Brugger Cc: Seiya Wang (王迺君), Greg Kroah-Hartman, Rob Herring, Wim Van Sebroeck, Guenter Roeck, linux-serial, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-watchdog, srv_heupstream On Fri, 2020-07-24 at 06:00 +0800, Matthias Brugger wrote: > > On 23/07/2020 11:07, Seiya Wang wrote: > > From: Crystal Guo <crystal.guo@mediatek.com> > > > > add driver setting to support mt8192 wdt > > > > Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> > > --- > > drivers/watchdog/mtk_wdt.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c > > index d6a6393f609d..ad23596170af 100644 > > --- a/drivers/watchdog/mtk_wdt.c > > +++ b/drivers/watchdog/mtk_wdt.c > > @@ -76,6 +76,10 @@ static const struct mtk_wdt_data mt8183_data = { > > .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, > > }; > > > > +static const struct mtk_wdt_data mt8192_data = { > > + .toprgu_sw_rst_num = 23, > > Should be defined in include/dt-bindings/reset-controller/mt8192-resets.h mt8xxx-resets.h actually just used to define TOPRGU_SW_RST_NUM, may be it's more easier to maintain by define it at OF data directly, instead of resubmit the mt8xxx-reset.h and add "include/dt-bindings/reset-controller/mt8xxx-resets.h" at mtk_wdt.c. Regards Crystal Guo > > > +}; > > + > > static int toprgu_reset_update(struct reset_controller_dev *rcdev, > > unsigned long id, bool assert) > > { > > @@ -322,6 +326,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = { > > { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, > > { .compatible = "mediatek,mt6589-wdt" }, > > { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, > > + { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, > > { /* sentinel */ } > > }; > > MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); > > ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 4/4] dt-binding: mediatek: mt8192: update mtk-wdt document 2020-07-23 9:07 [PATCH 0/4] Add basic node support for Mediatek MT8192 SoC Seiya Wang ` (2 preceding siblings ...) 2020-07-23 9:07 ` [PATCH 3/4] watchdog: mt8192: add wdt support Seiya Wang @ 2020-07-23 9:07 ` Seiya Wang 2020-07-23 21:29 ` Rob Herring 3 siblings, 1 reply; 11+ messages in thread From: Seiya Wang @ 2020-07-23 9:07 UTC (permalink / raw) To: Greg Kroah-Hartman, Rob Herring, Matthias Brugger, Wim Van Sebroeck, Guenter Roeck Cc: linux-serial, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-watchdog, srv_heupstream, Crystal Guo From: Crystal Guo <crystal.guo@mediatek.com> update mtk-wdt document for MT8192 platform Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 4dd36bd3f1ad..d760ca8a630e 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -12,6 +12,8 @@ Required properties: "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 + "mediatek,mt8192-wdt": for MT8192 + - reg : Specifies base physical address and size of the registers. -- 2.14.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 4/4] dt-binding: mediatek: mt8192: update mtk-wdt document 2020-07-23 9:07 ` [PATCH 4/4] dt-binding: mediatek: mt8192: update mtk-wdt document Seiya Wang @ 2020-07-23 21:29 ` Rob Herring 2020-07-23 22:02 ` Matthias Brugger 0 siblings, 1 reply; 11+ messages in thread From: Rob Herring @ 2020-07-23 21:29 UTC (permalink / raw) To: Seiya Wang Cc: Greg Kroah-Hartman, Matthias Brugger, Wim Van Sebroeck, Guenter Roeck, linux-serial, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-watchdog, srv_heupstream, Crystal Guo On Thu, Jul 23, 2020 at 05:07:31PM +0800, Seiya Wang wrote: > From: Crystal Guo <crystal.guo@mediatek.com> > > update mtk-wdt document for MT8192 platform > > Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> > --- > Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > index 4dd36bd3f1ad..d760ca8a630e 100644 > --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > @@ -12,6 +12,8 @@ Required properties: > "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 > "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183 > "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 > + "mediatek,mt8192-wdt": for MT8192 > + So, not compatible with "mediatek,mt6589-wdt"? Is so, perhaps summarize what the differences are. > > - reg : Specifies base physical address and size of the registers. > > -- > 2.14.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 4/4] dt-binding: mediatek: mt8192: update mtk-wdt document 2020-07-23 21:29 ` Rob Herring @ 2020-07-23 22:02 ` Matthias Brugger 2020-07-24 6:35 ` Crystal Guo 0 siblings, 1 reply; 11+ messages in thread From: Matthias Brugger @ 2020-07-23 22:02 UTC (permalink / raw) To: Rob Herring, Seiya Wang Cc: Greg Kroah-Hartman, Wim Van Sebroeck, Guenter Roeck, linux-serial, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-watchdog, srv_heupstream, Crystal Guo On 23/07/2020 23:29, Rob Herring wrote: > On Thu, Jul 23, 2020 at 05:07:31PM +0800, Seiya Wang wrote: >> From: Crystal Guo <crystal.guo@mediatek.com> >> >> update mtk-wdt document for MT8192 platform >> >> Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> >> --- >> Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt >> index 4dd36bd3f1ad..d760ca8a630e 100644 >> --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt >> +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt >> @@ -12,6 +12,8 @@ Required properties: >> "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 >> "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183 >> "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 >> + "mediatek,mt8192-wdt": for MT8192 >> + > > So, not compatible with "mediatek,mt6589-wdt"? Is so, perhaps summarize > what the differences are. > Hm, looks to me as if the binding description for mt2712 and mt8183 isn't correct, as we have a OF data just as we have for mt8192 now. Could you fix this in a separate patch? Regards, Matthias >> >> - reg : Specifies base physical address and size of the registers. >> >> -- >> 2.14.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 4/4] dt-binding: mediatek: mt8192: update mtk-wdt document 2020-07-23 22:02 ` Matthias Brugger @ 2020-07-24 6:35 ` Crystal Guo 0 siblings, 0 replies; 11+ messages in thread From: Crystal Guo @ 2020-07-24 6:35 UTC (permalink / raw) To: Matthias Brugger Cc: Rob Herring, Seiya Wang (王迺君), Greg Kroah-Hartman, Wim Van Sebroeck, Guenter Roeck, linux-serial, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-watchdog, srv_heupstream On Fri, 2020-07-24 at 06:02 +0800, Matthias Brugger wrote: > > On 23/07/2020 23:29, Rob Herring wrote: > > On Thu, Jul 23, 2020 at 05:07:31PM +0800, Seiya Wang wrote: > >> From: Crystal Guo <crystal.guo@mediatek.com> > >> > >> update mtk-wdt document for MT8192 platform > >> > >> Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> > >> --- > >> Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 2 ++ > >> 1 file changed, 2 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > >> index 4dd36bd3f1ad..d760ca8a630e 100644 > >> --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > >> +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > >> @@ -12,6 +12,8 @@ Required properties: > >> "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 > >> "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183 > >> "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 > >> + "mediatek,mt8192-wdt": for MT8192 > >> + > > > > So, not compatible with "mediatek,mt6589-wdt"? Is so, perhaps summarize > > what the differences are. > > > > Hm, looks to me as if the binding description for mt2712 and mt8183 isn't > correct, as we have a OF data just as we have for mt8192 now. Could you fix this > in a separate patch? > > Regards, > Matthias > > Besides watchdog, mt8192 toprgu module also provide sub-system software reset features. > mt2712 and mt8183 are same as mt8192. But mt6589 not support sub-system software reset. > > >> > >> - reg : Specifies base physical address and size of the registers. > >> > >> -- > >> 2.14.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-07-24 7:03 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-07-23 9:07 [PATCH 0/4] Add basic node support for Mediatek MT8192 SoC Seiya Wang 2020-07-23 9:07 ` [PATCH 1/4] arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile Seiya Wang 2020-07-23 9:07 ` [PATCH 2/4] dt-bindings: serial: Add compatible for Mediatek MT8192 Seiya Wang 2020-07-23 21:28 ` Rob Herring 2020-07-23 9:07 ` [PATCH 3/4] watchdog: mt8192: add wdt support Seiya Wang 2020-07-23 22:00 ` Matthias Brugger 2020-07-24 7:02 ` Crystal Guo 2020-07-23 9:07 ` [PATCH 4/4] dt-binding: mediatek: mt8192: update mtk-wdt document Seiya Wang 2020-07-23 21:29 ` Rob Herring 2020-07-23 22:02 ` Matthias Brugger 2020-07-24 6:35 ` Crystal Guo
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).