From mboxrd@z Thu Jan  1 00:00:00 1970
From: Rob Landley <rob@landley.net>
Date: Wed, 15 Apr 2020 23:21:01 +0000
Subject: Re: [PATCH] serial: sh-sci: Make sure status register SCxSR is read in correct sequence
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To: Geert Uytterhoeven <geert@linux-m68k.org>, "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>, Kazuhiro Fujita <kazuhiro.fujita.jg@renesas.com>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jiri Slaby <jslaby@suse.com>, "open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Hao Bui <hao.bui.yg@renesas.com>, KAZUMI HARADA <kazumi.harada.rh@renesas.com>, Sasha Levin <sashal@kernel.org>, Chris Brandt <Chris.Brandt@renesas.com>, Magnus Damm <magnus.damm@gmail.com>, Linux-sh list <linux-sh@vger.kernel.org>, John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>

On 4/15/20 7:36 AM, Geert Uytterhoeven wrote:
>> Let's wait a bit, we're in the middle of the merge window anyway.
>> Probably we can get it tested on SuperH during the coming weeks.
> 
> Anyone with a real (not qemu) SuperH system who can do the basic "stty evenp"
> tests above, and report back to us?
> Thanks a lot!
The j-core boards use either uartlite or 16550a for serial, and neither of my
legacy sh4 boxes is easily accessible right now. But if nobody manages to test
this before next merge window poke me and I can set one up.

Rob