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From: (Vineet Gupta)
Subject: [PATCH 3/6] ARC: mm: TLB Miss optim: avoid re-reading ECR
Date: Mon, 16 Sep 2019 14:32:04 -0700
Message-ID: <> (raw)
In-Reply-To: <>

For setting PTE Dirty bit, reuse the prior test for ST miss.

No need to reload ECR and test for ST cause code as the prev
condition code is still valid (uncloberred)

Signed-off-by: Vineet Gupta <vgupta at>
 arch/arc/mm/tlbex.S | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index 110c72536e8b..4c88148d4cd1 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -380,9 +380,7 @@ ENTRY(EV_TLBMissD)
 	; UPDATE_PTE: Let Linux VM know that page was accessed/dirty
-	lr      r3, [ecr]
 	or      r0, r0, _PAGE_ACCESSED        ; Accessed bit always
-	btst_s  r3,  ECR_C_BIT_DTLB_ST_MISS   ; See if it was a Write Access ?   r0, r0, _PAGE_DIRTY           ; if Write, set Dirty bit as well
 	st_s    r0, [r1]                      ; Write back PTE

  parent reply index

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-16 21:32 [PATCH 0/6] ARC MMU code updates Vineet.Gupta1
2019-09-16 21:32 ` [PATCH 1/6] ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg Vineet.Gupta1
2019-09-16 21:32 ` [PATCH 2/6] ARCv2: mm: TLB Miss optim: Use double world load/stores LDD/STD Vineet.Gupta1
2019-09-16 21:32 ` Vineet.Gupta1 [this message]
2019-09-16 23:36   ` [PATCH 3/6] ARC: mm: TLB Miss optim: avoid re-reading ECR Alexey.Brodkin
2019-09-17 21:08     ` vineetg76
2019-09-16 21:32 ` [PATCH 4/6] ARC: mm: tlb flush optim: Make TLBWriteNI fallback to TLBWrite if not available Vineet.Gupta1
2019-09-16 21:32 ` [PATCH 5/6] ARC: mm: tlb flush optim: elide repeated uTLB invalidate in loop Vineet.Gupta1
2019-09-16 21:32 ` [PATCH 6/6] ARC: mm: tlb flush optim: elide redundant uTLB invalidates for MMUv3 Vineet.Gupta1

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