From: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
To: linux-sparse@vger.kernel.org
Cc: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
Subject: [PATCH 2/3] riscv: parse '-march=....'
Date: Wed, 8 Jul 2020 23:48:08 +0200 [thread overview]
Message-ID: <20200708214810.56214-3-luc.vanoostenryck@gmail.com> (raw)
In-Reply-To: <20200708214810.56214-1-luc.vanoostenryck@gmail.com>
The RISC-V architecture has quite a bit of extensions.
Some of these correspond to a predefined macro and thus
parsing correctly the '-march' flag can be important.
So, teach sparse how to parse this flag for RISC-V.
Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
---
target-riscv.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++
target.h | 1 +
2 files changed, 81 insertions(+)
diff --git a/target-riscv.c b/target-riscv.c
index d68fb585c254..9431ebc9cabb 100644
--- a/target-riscv.c
+++ b/target-riscv.c
@@ -1,7 +1,80 @@
+#include "lib.h"
#include "symbol.h"
#include "target.h"
#include "machine.h"
+#include <string.h>
+#define RISCV_32BIT (1 << 0)
+#define RISCV_64BIT (1 << 1)
+#define RISCV_MUL (1 << 2)
+#define RISCV_DIV (1 << 3)
+#define RISCV_ATOMIC (1 << 4)
+#define RISCV_FLOAT (1 << 5)
+#define RISCV_DOUBLE (1 << 6)
+#define RISCV_FDIV (1 << 7)
+#define RISCV_COMP (1 << 8)
+#define RISCV_EMBD (1 << 9)
+#define RISCV_FPU (RISCV_FLOAT|RISCV_DOUBLE|RISCV_FDIV)
+#define RISCV_GENERIC (RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU)
+
+static unsigned int riscv_flags;
+
+static void parse_march_riscv(const char *arg)
+{
+ static struct {
+ const char *pattern;
+ unsigned int flags;
+ } basic_sets[] = {
+ { "rv32i", RISCV_32BIT },
+ { "rv32e", RISCV_32BIT|RISCV_EMBD },
+ { "rv32g", RISCV_32BIT|RISCV_GENERIC },
+ { "rv64i", RISCV_64BIT },
+ { "rv64g", RISCV_64BIT|RISCV_GENERIC },
+ }, extensions[] = {
+ { "m", RISCV_MUL|RISCV_DIV },
+ { "a", RISCV_ATOMIC },
+ { "f", RISCV_FLOAT|RISCV_FDIV },
+ { "d", RISCV_DOUBLE|RISCV_FDIV },
+ { "g", RISCV_GENERIC },
+ { "q", 0 },
+ { "l", 0 },
+ { "c", RISCV_COMP },
+ { "b", 0 },
+ { "j", 0 },
+ { "t", 0 },
+ { "p", 0 },
+ { "v", 0 },
+ { "n", 0 },
+ { "h", 0 },
+ { "s", 0 },
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(basic_sets); i++) {
+ const char *pat = basic_sets[i].pattern;
+ size_t len = strlen(pat);
+
+ if (!strncmp(arg, pat, len)) {
+ riscv_flags |= basic_sets[i].flags;
+ arg += len;
+ goto ext;
+ }
+ }
+ die("invalid argument to '-march': '%s'\n", arg);
+
+ext:
+ for (i = 0; i < ARRAY_SIZE(extensions); i++) {
+ const char *pat = extensions[i].pattern;
+ size_t len = strlen(pat);
+
+ if (!strncmp(arg, pat, len)) {
+ riscv_flags |= extensions[i].flags;
+ arg += len;
+ }
+ }
+ if (arg[0])
+ die("invalid argument to '-march': '%s'\n", arg);
+}
static void init_riscv(const struct target *self)
{
@@ -9,6 +82,9 @@ static void init_riscv(const struct target *self)
arch_cmodel = CMODEL_MEDLOW;
if (fpic)
arch_cmodel = CMODEL_PIC;
+
+ if (riscv_flags == 0)
+ riscv_flags = self->flags;
}
static void predefine_riscv(const struct target *self)
@@ -32,11 +108,13 @@ const struct target target_riscv32 = {
.bitness = ARCH_LP32,
.big_endian = 0,
.unsigned_char = 1,
+ .flags = RISCV_32BIT|RISCV_GENERIC|RISCV_COMP,
.target_64bit = &target_riscv64,
.init = init_riscv,
.predefine = predefine_riscv,
+ .parse_march = parse_march_riscv,
};
const struct target target_riscv64 = {
@@ -45,9 +123,11 @@ const struct target target_riscv64 = {
.big_endian = 0,
.unsigned_char = 1,
.has_int128 = 1,
+ .flags = RISCV_64BIT|RISCV_GENERIC|RISCV_COMP,
.target_32bit = &target_riscv32,
.init = init_riscv,
.predefine = predefine_riscv,
+ .parse_march = parse_march_riscv,
};
diff --git a/target.h b/target.h
index 54e97e83b10d..76b7d12318c6 100644
--- a/target.h
+++ b/target.h
@@ -63,6 +63,7 @@ struct target {
unsigned int unsigned_char:1;
unsigned int size_t_long:1;
unsigned int has_int128:1;
+ unsigned long flags;
struct symbol *wchar;
struct symbol *wint;
--
2.27.0
next prev parent reply other threads:[~2020-07-08 21:48 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-08 21:48 [PATCH 0/3] teach sparse about the '-march' for RISC-V Luc Van Oostenryck
2020-07-08 21:48 ` [PATCH 1/3] arch: teach sparse about the '-march' option Luc Van Oostenryck
2020-07-08 21:48 ` Luc Van Oostenryck [this message]
2020-07-08 21:48 ` [PATCH 3/3] riscv: add the predefines for the extensions Luc Van Oostenryck
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