From: <Tudor.Ambarus@microchip.com>
To: <p.yadav@ti.com>, <miquel.raynal@bootlin.com>
Cc: <richard@nod.at>, <vigneshr@ti.com>, <michael@walle.cc>,
<linux-mtd@lists.infradead.org>, <broonie@kernel.org>,
<linux-spi@vger.kernel.org>, <robh+dt@kernel.org>,
<devicetree@vger.kernel.org>, <thomas.petazzoni@bootlin.com>,
<monstr@monstr.eu>
Subject: Re: [PATCH v3 2/3] spi: dt-bindings: Describe stacked/parallel memories modes
Date: Tue, 7 Dec 2021 07:35:59 +0000 [thread overview]
Message-ID: <0d97a420-685e-5120-3c09-d433382c02aa@microchip.com> (raw)
In-Reply-To: <20211207071406.c2ajc3shqybevvjj@ti.com>
On 12/7/21 9:14 AM, Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 06/12/21 10:59AM, Miquel Raynal wrote:
>> Describe two new memories modes:
>> - A stacked mode when the bus is common but the address space extended
>> with an additinals wires.
>> - A parallel mode with parallel busses accessing parallel flashes where
>> the data is spread.
>>
>> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
>> ---
>> .../bindings/spi/spi-peripheral-props.yaml | 21 +++++++++++++++++++
>> 1 file changed, 21 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
>> index 5dd209206e88..13aa6a2374c9 100644
>> --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
>> +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
>> @@ -82,6 +82,27 @@ properties:
>> description:
>> Delay, in microseconds, after a write transfer.
>>
>> + stacked-memories:
>> + type: boolean
>
> I don't think a boolean is enough to completely describe the memory.
> Sure, you say the memories are stacked, but where do you specify when to
> switch the CS? They could be two 512 MiB memories, two 1 GiB memories,
> or one 512 MiB and one 256 MiB.
If the multi-die flash contains identical dies then the die boundary can be
determined with flash_size / number_of_cs. Are there any multi die flashes
with different types of dies?
>
>> + description: Several SPI memories can be wired in stacked mode.
>> + This basically means that either a device features several chip
>> + selects, or that different devices must be seen as a single
>> + bigger chip. This basically doubles (or more) the total address
>> + space with only a single additional wire, while still needing
>> + to repeat the commands when crossing a chip boundary. XIP is
>> + usually not supported in this mode.
>> +
>> + parallel-memories:
>> + type: boolean
>
> With this I assume both memories have to be the same size?
It looks like the assumption for both cases is that the dies are identical.
>
>> + description: Several SPI memories can be wired in parallel mode.
>> + The devices are physically on a different buses but will always
>> + act synchronously as each data word is spread across the
>> + different memories (eg. even bits are stored in one memory, odd
>> + bits in the other). This basically doubles the address space and
>> + the throughput while greatly complexifying the wiring because as
>> + many busses as devices must be wired. XIP is usually not
>> + supported in this mode.
>> +
>> # The controller specific properties go here.
>> allOf:
>> - $ref: cdns,qspi-nor-peripheral-props.yaml#
>> --
>> 2.27.0
>>
>
> --
> Regards,
> Pratyush Yadav
> Texas Instruments Inc.
>
next prev parent reply other threads:[~2021-12-07 7:36 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-06 9:59 [PATCH v3 0/3] Stacked/parallel memories bindings Miquel Raynal
2021-12-06 9:59 ` [PATCH v3 1/3] dt-bindings: mtd: spi-nor: Allow two CS per device Miquel Raynal
2021-12-07 7:16 ` Tudor.Ambarus
2021-12-07 8:44 ` Miquel Raynal
2021-12-06 9:59 ` [PATCH v3 2/3] spi: dt-bindings: Describe stacked/parallel memories modes Miquel Raynal
2021-12-06 21:22 ` Rob Herring
2021-12-10 20:07 ` Miquel Raynal
2021-12-07 7:14 ` Pratyush Yadav
2021-12-07 7:35 ` Tudor.Ambarus [this message]
2021-12-07 7:43 ` Tudor.Ambarus
2021-12-07 7:47 ` Tudor.Ambarus
2021-12-07 7:57 ` Pratyush Yadav
2021-12-07 8:37 ` Miquel Raynal
2021-12-06 9:59 ` [PATCH v3 3/3] spi: dt-bindings: Add an example with two stacked flashes Miquel Raynal
2021-12-06 21:31 ` Rob Herring
2021-12-06 21:31 ` [PATCH v3 0/3] Stacked/parallel memories bindings Rob Herring
2021-12-07 14:31 ` Mark Brown
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=0d97a420-685e-5120-3c09-d433382c02aa@microchip.com \
--to=tudor.ambarus@microchip.com \
--cc=broonie@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=linux-spi@vger.kernel.org \
--cc=michael@walle.cc \
--cc=miquel.raynal@bootlin.com \
--cc=monstr@monstr.eu \
--cc=p.yadav@ti.com \
--cc=richard@nod.at \
--cc=robh+dt@kernel.org \
--cc=thomas.petazzoni@bootlin.com \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).