[PATCH 0/6] Add interconnect support to UART, I2C, SPI and QSPI

[PATCH 0/6] Add interconnect support to UART, I2C, SPI and QSPI

[Akash Asthana]

dt-binding patch for UART, I2C and SPI.
 - https://patchwork.kernel.org/patch/11385965/ [Convert QUP bindings
	to YAML and add ICC, pin swap doc]

dt-binding patch for QSPI.
 - https://patchwork.kernel.org/cover/11386003/ [Convert QSPI binding
	to YAML and add interconnect doc]

Akash Asthana (6):
  soc: qcom: geni: Support for ICC voting
  tty: serial: qcom_geni_serial: Add interconnect support
  i2c: i2c-qcom-geni: Add interconnect support
  spi: spi-geni-qcom: Add interconnect support
  spi: spi-qcom-qspi: Add interconnect support
  arm64: dts: sc7180: Add interconnect for QUP and QSPI

 arch/arm64/boot/dts/qcom/sc7180.dtsi  | 199 ++++++++++++++++++++++++++++++++++
 drivers/i2c/busses/i2c-qcom-geni.c    |  84 +++++++++++++-
 drivers/spi/spi-geni-qcom.c           |  65 ++++++++++-
 drivers/spi/spi-qcom-qspi.c           |  38 ++++++-
 drivers/tty/serial/qcom_geni_serial.c |  84 ++++++++++++--
 include/linux/qcom-geni-se.h          |  31 ++++++
 6 files changed, 481 insertions(+), 20 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

[PATCH 1/6] soc: qcom: geni: Support for ICC voting

[Akash Asthana]

Add necessary enums, macros and structure variables to support ICC BW
voting from individual SE drivers.

Signed-off-by: Akash Asthana <akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 include/linux/qcom-geni-se.h | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h
index dd46494..b0adbfb 100644
--- a/include/linux/qcom-geni-se.h
+++ b/include/linux/qcom-geni-se.h
@@ -6,6 +6,8 @@
 #ifndef _LINUX_QCOM_GENI_SE
 #define _LINUX_QCOM_GENI_SE
 
+#include <linux/interconnect.h>
+
 /* Transfer mode supported by GENI Serial Engines */
 enum geni_se_xfer_mode {
 	GENI_SE_INVALID,
@@ -22,6 +24,13 @@ enum geni_se_protocol_type {
 	GENI_SE_I3C,
 };
 
+/* Interconnect paths for GENI */
+enum geni_se_icc_path {
+	GENI_TO_CORE,
+	CPU_TO_GENI,
+	GENI_TO_DDR
+};
+
 struct geni_wrapper;
 struct clk;
 
@@ -33,6 +42,13 @@ struct clk;
  * @clk:		Handle to the core serial engine clock
  * @num_clk_levels:	Number of valid clock levels in clk_perf_tbl
  * @clk_perf_tbl:	Table of clock frequency input to serial engine clock
+ * @icc_path:		Array of interconnect path handles
+ * @avg_bw_core:	Average bus bandwidth value for QUP core 2x clock
+ * @peak_bw_core:	Peak bus bandwidth value for QUP core 2x clock
+ * @avg_bw_cpu:		Average bus bandwidth value for CPU
+ * @peak_bw_cpu:	Peak bus bandwidth value for CPU
+ * @avg_bw_ddr:		Average bus bandwidth value for DDR
+ * @peak_bw_ddr:	Peak bus bandwidth value for DDR
  */
 struct geni_se {
 	void __iomem *base;
@@ -41,6 +57,13 @@ struct geni_se {
 	struct clk *clk;
 	unsigned int num_clk_levels;
 	unsigned long *clk_perf_tbl;
+	struct icc_path *icc_path[3];
+	unsigned int avg_bw_core;
+	unsigned int peak_bw_core;
+	unsigned int avg_bw_cpu;
+	unsigned int peak_bw_cpu;
+	unsigned int avg_bw_ddr;
+	unsigned int peak_bw_ddr;
 };
 
 /* Common SE registers */
@@ -229,6 +252,14 @@ struct geni_se {
 #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
 #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
 
+/* Core 2X clock frequency to BCM threshold mapping */
+#define CORE_2X_19_2_MHZ		960
+#define CORE_2X_50_MHZ			2500
+#define CORE_2X_100_MHZ			5000
+#define CORE_2X_150_MHZ			7500
+#define CORE_2X_200_MHZ			10000
+#define CORE_2X_236_MHZ			16383
+
 #if IS_ENABLED(CONFIG_QCOM_GENI_SE)
 
 u32 geni_se_get_qup_hw_version(struct geni_se *se);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

Re: [PATCH 1/6] soc: qcom: geni: Support for ICC voting

[Bjorn Andersson]

On Mon 17 Feb 05:30 PST 2020, Akash Asthana wrote:

> Add necessary enums, macros and structure variables to support ICC BW
> voting from individual SE drivers.
> 
> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> ---
>  include/linux/qcom-geni-se.h | 31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h
> index dd46494..b0adbfb 100644
> --- a/include/linux/qcom-geni-se.h
> +++ b/include/linux/qcom-geni-se.h
> @@ -6,6 +6,8 @@
>  #ifndef _LINUX_QCOM_GENI_SE
>  #define _LINUX_QCOM_GENI_SE
>  
> +#include <linux/interconnect.h>
> +
>  /* Transfer mode supported by GENI Serial Engines */
>  enum geni_se_xfer_mode {
>  	GENI_SE_INVALID,
> @@ -22,6 +24,13 @@ enum geni_se_protocol_type {
>  	GENI_SE_I3C,
>  };
>  
> +/* Interconnect paths for GENI */
> +enum geni_se_icc_path {
> +	GENI_TO_CORE,
> +	CPU_TO_GENI,
> +	GENI_TO_DDR
> +};
> +
>  struct geni_wrapper;
>  struct clk;
>  
> @@ -33,6 +42,13 @@ struct clk;
>   * @clk:		Handle to the core serial engine clock
>   * @num_clk_levels:	Number of valid clock levels in clk_perf_tbl
>   * @clk_perf_tbl:	Table of clock frequency input to serial engine clock
> + * @icc_path:		Array of interconnect path handles
> + * @avg_bw_core:	Average bus bandwidth value for QUP core 2x clock
> + * @peak_bw_core:	Peak bus bandwidth value for QUP core 2x clock
> + * @avg_bw_cpu:		Average bus bandwidth value for CPU
> + * @peak_bw_cpu:	Peak bus bandwidth value for CPU
> + * @avg_bw_ddr:		Average bus bandwidth value for DDR
> + * @peak_bw_ddr:	Peak bus bandwidth value for DDR
>   */
>  struct geni_se {
>  	void __iomem *base;
> @@ -41,6 +57,13 @@ struct geni_se {
>  	struct clk *clk;
>  	unsigned int num_clk_levels;
>  	unsigned long *clk_perf_tbl;
> +	struct icc_path *icc_path[3];

In all cases you refer to icc_path[IDENIFIER], so just give the three
paths individual members and drop the enum above.

Reards,
Bjorn

> +	unsigned int avg_bw_core;
> +	unsigned int peak_bw_core;
> +	unsigned int avg_bw_cpu;
> +	unsigned int peak_bw_cpu;
> +	unsigned int avg_bw_ddr;
> +	unsigned int peak_bw_ddr;
>  };
>  
>  /* Common SE registers */
> @@ -229,6 +252,14 @@ struct geni_se {
>  #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
>  #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
>  
> +/* Core 2X clock frequency to BCM threshold mapping */
> +#define CORE_2X_19_2_MHZ		960
> +#define CORE_2X_50_MHZ			2500
> +#define CORE_2X_100_MHZ			5000
> +#define CORE_2X_150_MHZ			7500
> +#define CORE_2X_200_MHZ			10000
> +#define CORE_2X_236_MHZ			16383
> +
>  #if IS_ENABLED(CONFIG_QCOM_GENI_SE)
>  
>  u32 geni_se_get_qup_hw_version(struct geni_se *se);
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

Re: [PATCH 1/6] soc: qcom: geni: Support for ICC voting

[Akash Asthana]

Hi Bjorn,

>>   	struct clk *clk;
>>   	unsigned int num_clk_levels;
>>   	unsigned long *clk_perf_tbl;
>> +	struct icc_path *icc_path[3];
> In all cases you refer to icc_path[IDENIFIER], so just give the three
> paths individual members and drop the enum above.
>
> Reards,
> Bjorn

Ok

Thanks for reviewing.

Regards,

Akash

>
>> +	unsigned int avg_bw_core;
>> Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

[PATCH 2/6] tty: serial: qcom_geni_serial: Add interconnect support

[Akash Asthana]

Get the interconnect paths for Uart based Serial Engine device
and vote according to the baud rate requirement of the driver.

Signed-off-by: Akash Asthana <akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 drivers/tty/serial/qcom_geni_serial.c | 84 ++++++++++++++++++++++++++++++-----
 1 file changed, 74 insertions(+), 10 deletions(-)

diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
index 191abb1..a8fb2b7 100644
--- a/drivers/tty/serial/qcom_geni_serial.c
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -174,6 +174,35 @@ static struct qcom_geni_serial_port qcom_geni_console_port = {
 	},
 };
 
+static int geni_serial_icc_get(struct geni_se *se)
+{
+	if (!se)
+		return -EINVAL;
+
+	se->icc_path[GENI_TO_CORE] = of_icc_get(se->dev, "qup-core");
+	if (IS_ERR(se->icc_path[GENI_TO_CORE]))
+		return PTR_ERR(se->icc_path[GENI_TO_CORE]);
+
+	se->icc_path[CPU_TO_GENI] = of_icc_get(se->dev, "qup-config");
+	if (IS_ERR(se->icc_path[CPU_TO_GENI])) {
+		icc_put(se->icc_path[GENI_TO_CORE]);
+		se->icc_path[GENI_TO_CORE] = NULL;
+		return PTR_ERR(se->icc_path[CPU_TO_GENI]);
+	}
+
+	return 0;
+}
+
+void geni_serial_icc_put(struct geni_se *se)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(se->icc_path); i++) {
+		icc_put(se->icc_path[i]);
+		se->icc_path[i] = NULL;
+	}
+}
+
 static int qcom_geni_serial_request_port(struct uart_port *uport)
 {
 	struct platform_device *pdev = to_platform_device(uport->dev);
@@ -949,6 +978,12 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
 	ser_clk_cfg = SER_CLK_EN;
 	ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
 
+	/* Put BW vote only on CPU path as driver supports FIFO mode only */
+	port->se.avg_bw_cpu = Bps_to_icc(baud);
+	port->se.peak_bw_cpu = Bps_to_icc(2 * baud);
+	icc_set_bw(port->se.icc_path[CPU_TO_GENI], port->se.avg_bw_cpu,
+			port->se.peak_bw_cpu);
+
 	/* parity */
 	tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
 	tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
@@ -1179,11 +1214,20 @@ static void qcom_geni_serial_pm(struct uart_port *uport,
 	if (old_state == UART_PM_STATE_UNDEFINED)
 		old_state = UART_PM_STATE_OFF;
 
-	if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
+	if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
+		/* Put BW vote for core clocks and CPU */
+		icc_set_bw(port->se.icc_path[GENI_TO_CORE],
+			port->se.avg_bw_core, port->se.peak_bw_core);
+		icc_set_bw(port->se.icc_path[CPU_TO_GENI], port->se.avg_bw_cpu,
+			port->se.peak_bw_cpu);
 		geni_se_resources_on(&port->se);
-	else if (new_state == UART_PM_STATE_OFF &&
-			old_state == UART_PM_STATE_ON)
+	} else if (new_state == UART_PM_STATE_OFF &&
+			old_state == UART_PM_STATE_ON) {
 		geni_se_resources_off(&port->se);
+		/* Remove BW vote from core clocks and CPU */
+		icc_set_bw(port->se.icc_path[GENI_TO_CORE], 0, 0);
+		icc_set_bw(port->se.icc_path[CPU_TO_GENI], 0, 0);
+	}
 }
 
 static const struct uart_ops qcom_geni_console_pops = {
@@ -1274,15 +1318,30 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
 	port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
 	port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
 
+	ret = geni_serial_icc_get(&port->se);
+	if (ret)
+		return ret;
+	/* Set the bus quota to a reasonable value */
+	port->se.avg_bw_core = console ? Bps_to_icc(1000) :
+		Bps_to_icc(CORE_2X_50_MHZ);
+	port->se.peak_bw_core = console ? Bps_to_icc(1000) :
+		Bps_to_icc(CORE_2X_100_MHZ);
+	port->se.avg_bw_cpu = Bps_to_icc(1000);
+	port->se.avg_bw_cpu = Bps_to_icc(1000);
+
 	port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
 			"qcom_geni_serial_%s%d",
 			uart_console(uport) ? "console" : "uart", uport->line);
-	if (!port->name)
-		return -ENOMEM;
+	if (!port->name) {
+		ret = -ENOMEM;
+		goto geni_serial_put_icc;
+	}
 
 	irq = platform_get_irq(pdev, 0);
-	if (irq < 0)
-		return irq;
+	if (irq < 0) {
+		ret = irq;
+		goto geni_serial_put_icc;
+	}
 	uport->irq = irq;
 	uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
 
@@ -1295,7 +1354,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
 
 	ret = uart_add_one_port(drv, uport);
 	if (ret)
-		return ret;
+		goto geni_serial_put_icc;
 
 	irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
 	ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
@@ -1303,7 +1362,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
 	if (ret) {
 		dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
 		uart_remove_one_port(drv, uport);
-		return ret;
+		goto geni_serial_put_icc;
 	}
 
 	/*
@@ -1320,11 +1379,15 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
 		if (ret) {
 			device_init_wakeup(&pdev->dev, false);
 			uart_remove_one_port(drv, uport);
-			return ret;
+			goto geni_serial_put_icc;
 		}
 	}
 
 	return 0;
+
+geni_serial_put_icc:
+	geni_serial_icc_put(&port->se);
+	return ret;
 }
 
 static int qcom_geni_serial_remove(struct platform_device *pdev)
@@ -1335,6 +1398,7 @@ static int qcom_geni_serial_remove(struct platform_device *pdev)
 	dev_pm_clear_wake_irq(&pdev->dev);
 	device_init_wakeup(&pdev->dev, false);
 	uart_remove_one_port(drv, &port->uport);
+	geni_serial_icc_put(&port->se);
 
 	return 0;
 }
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

Re: [PATCH 2/6] tty: serial: qcom_geni_serial: Add interconnect support

[Greg KH]

On Mon, Feb 17, 2020 at 07:00:01PM +0530, Akash Asthana wrote:
> Get the interconnect paths for Uart based Serial Engine device
> and vote according to the baud rate requirement of the driver.
> 
> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> ---
>  drivers/tty/serial/qcom_geni_serial.c | 84 ++++++++++++++++++++++++++++++-----
>  1 file changed, 74 insertions(+), 10 deletions(-)

Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Re: [PATCH 2/6] tty: serial: qcom_geni_serial: Add interconnect support

[Bjorn Andersson]

On Mon 17 Feb 05:30 PST 2020, Akash Asthana wrote:

> Get the interconnect paths for Uart based Serial Engine device
> and vote according to the baud rate requirement of the driver.
> 
> Signed-off-by: Akash Asthana <akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>  drivers/tty/serial/qcom_geni_serial.c | 84 ++++++++++++++++++++++++++++++-----
>  1 file changed, 74 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
> index 191abb1..a8fb2b7 100644
> --- a/drivers/tty/serial/qcom_geni_serial.c
> +++ b/drivers/tty/serial/qcom_geni_serial.c
> @@ -174,6 +174,35 @@ static struct qcom_geni_serial_port qcom_geni_console_port = {
>  	},
>  };
>  
> +static int geni_serial_icc_get(struct geni_se *se)
> +{
> +	if (!se)

If se == NULL the kernel has already oopsed as it dereferenced port->se
a few lines before calling this function.

> +		return -EINVAL;
> +
> +	se->icc_path[GENI_TO_CORE] = of_icc_get(se->dev, "qup-core");
> +	if (IS_ERR(se->icc_path[GENI_TO_CORE]))
> +		return PTR_ERR(se->icc_path[GENI_TO_CORE]);
> +
> +	se->icc_path[CPU_TO_GENI] = of_icc_get(se->dev, "qup-config");
> +	if (IS_ERR(se->icc_path[CPU_TO_GENI])) {
> +		icc_put(se->icc_path[GENI_TO_CORE]);
> +		se->icc_path[GENI_TO_CORE] = NULL;

You're going to fail probe when this happens, so why the need to reset
this path?

> +		return PTR_ERR(se->icc_path[CPU_TO_GENI]);
> +	}
> +
> +	return 0;
> +}
> +
> +void geni_serial_icc_put(struct geni_se *se)
> +{
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(se->icc_path); i++) {
> +		icc_put(se->icc_path[i]);

In geni_serial_icc_get() you hard open code this loop, so why not do the
same here, to maintain some symmetry.

> +		se->icc_path[i] = NULL;

Again, what's the purpose of this clear?

> +	}
> +}
> +
>  static int qcom_geni_serial_request_port(struct uart_port *uport)
>  {
>  	struct platform_device *pdev = to_platform_device(uport->dev);
> @@ -949,6 +978,12 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
>  	ser_clk_cfg = SER_CLK_EN;
>  	ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
>  
> +	/* Put BW vote only on CPU path as driver supports FIFO mode only */
> +	port->se.avg_bw_cpu = Bps_to_icc(baud);
> +	port->se.peak_bw_cpu = Bps_to_icc(2 * baud);
> +	icc_set_bw(port->se.icc_path[CPU_TO_GENI], port->se.avg_bw_cpu,
> +			port->se.peak_bw_cpu);
> +
>  	/* parity */
>  	tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
>  	tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
> @@ -1179,11 +1214,20 @@ static void qcom_geni_serial_pm(struct uart_port *uport,
>  	if (old_state == UART_PM_STATE_UNDEFINED)
>  		old_state = UART_PM_STATE_OFF;
>  
> -	if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
> +	if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
> +		/* Put BW vote for core clocks and CPU */
> +		icc_set_bw(port->se.icc_path[GENI_TO_CORE],
> +			port->se.avg_bw_core, port->se.peak_bw_core);
> +		icc_set_bw(port->se.icc_path[CPU_TO_GENI], port->se.avg_bw_cpu,
> +			port->se.peak_bw_cpu);
>  		geni_se_resources_on(&port->se);
> -	else if (new_state == UART_PM_STATE_OFF &&
> -			old_state == UART_PM_STATE_ON)
> +	} else if (new_state == UART_PM_STATE_OFF &&
> +			old_state == UART_PM_STATE_ON) {
>  		geni_se_resources_off(&port->se);
> +		/* Remove BW vote from core clocks and CPU */
> +		icc_set_bw(port->se.icc_path[GENI_TO_CORE], 0, 0);
> +		icc_set_bw(port->se.icc_path[CPU_TO_GENI], 0, 0);
> +	}
>  }
>  
>  static const struct uart_ops qcom_geni_console_pops = {
> @@ -1274,15 +1318,30 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
>  	port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
>  	port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
>  
> +	ret = geni_serial_icc_get(&port->se);
> +	if (ret)
> +		return ret;
> +	/* Set the bus quota to a reasonable value */
> +	port->se.avg_bw_core = console ? Bps_to_icc(1000) :
> +		Bps_to_icc(CORE_2X_50_MHZ);
> +	port->se.peak_bw_core = console ? Bps_to_icc(1000) :
> +		Bps_to_icc(CORE_2X_100_MHZ);
> +	port->se.avg_bw_cpu = Bps_to_icc(1000);
> +	port->se.avg_bw_cpu = Bps_to_icc(1000);
> +
>  	port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
>  			"qcom_geni_serial_%s%d",
>  			uart_console(uport) ? "console" : "uart", uport->line);
> -	if (!port->name)
> -		return -ENOMEM;
> +	if (!port->name) {
> +		ret = -ENOMEM;
> +		goto geni_serial_put_icc;

Rather than reworking the error handling like this, please introduce a
devm_icc_get() function in the interconnect API.

Regards,
Bjorn

> +	}
>  
>  	irq = platform_get_irq(pdev, 0);
> -	if (irq < 0)
> -		return irq;
> +	if (irq < 0) {
> +		ret = irq;
> +		goto geni_serial_put_icc;
> +	}
>  	uport->irq = irq;
>  	uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
>  
> @@ -1295,7 +1354,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
>  
>  	ret = uart_add_one_port(drv, uport);
>  	if (ret)
> -		return ret;
> +		goto geni_serial_put_icc;
>  
>  	irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
>  	ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
> @@ -1303,7 +1362,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
>  	if (ret) {
>  		dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
>  		uart_remove_one_port(drv, uport);
> -		return ret;
> +		goto geni_serial_put_icc;
>  	}
>  
>  	/*
> @@ -1320,11 +1379,15 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
>  		if (ret) {
>  			device_init_wakeup(&pdev->dev, false);
>  			uart_remove_one_port(drv, uport);
> -			return ret;
> +			goto geni_serial_put_icc;
>  		}
>  	}
>  
>  	return 0;
> +
> +geni_serial_put_icc:
> +	geni_serial_icc_put(&port->se);
> +	return ret;
>  }
>  
>  static int qcom_geni_serial_remove(struct platform_device *pdev)
> @@ -1335,6 +1398,7 @@ static int qcom_geni_serial_remove(struct platform_device *pdev)
>  	dev_pm_clear_wake_irq(&pdev->dev);
>  	device_init_wakeup(&pdev->dev, false);
>  	uart_remove_one_port(drv, &port->uport);
> +	geni_serial_icc_put(&port->se);
>  
>  	return 0;
>  }
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

Re: [PATCH 2/6] tty: serial: qcom_geni_serial: Add interconnect support

[Akash Asthana]

On 2/18/2020 8:45 AM, Bjorn Andersson wrote:
> On Mon 17 Feb 05:30 PST 2020, Akash Asthana wrote:
>
>> Get the interconnect paths for Uart based Serial Engine device
>> and vote according to the baud rate requirement of the driver.
>>
>> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
>> ---
>>   drivers/tty/serial/qcom_geni_serial.c | 84 ++++++++++++++++++++++++++++++-----
>>   1 file changed, 74 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
>> index 191abb1..a8fb2b7 100644
>> --- a/drivers/tty/serial/qcom_geni_serial.c
>> +++ b/drivers/tty/serial/qcom_geni_serial.c
>> @@ -174,6 +174,35 @@ static struct qcom_geni_serial_port qcom_geni_console_port = {
>>   	},
>>   };
>>   
>> +static int geni_serial_icc_get(struct geni_se *se)
>> +{
>> +	if (!se)
> If se == NULL the kernel has already oopsed as it dereferenced port->se
> a few lines before calling this function.
Ok, I will remove this check.
>> +		return -EINVAL;
>> +
>> +	se->icc_path[GENI_TO_CORE] = of_icc_get(se->dev, "qup-core");
>> +	if (IS_ERR(se->icc_path[GENI_TO_CORE]))
>> +		return PTR_ERR(se->icc_path[GENI_TO_CORE]);
>> +
>> +	se->icc_path[CPU_TO_GENI] = of_icc_get(se->dev, "qup-config");
>> +	if (IS_ERR(se->icc_path[CPU_TO_GENI])) {
>> +		icc_put(se->icc_path[GENI_TO_CORE]);
>> +		se->icc_path[GENI_TO_CORE] = NULL;
> You're going to fail probe when this happens, so why the need to reset
> this path?
Ok, I will remove this
>> +		return PTR_ERR(se->icc_path[CPU_TO_GENI]);
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +void geni_serial_icc_put(struct geni_se *se)
>> +{
>> +	int i;
>> +
>> +	for (i = 0; i < ARRAY_SIZE(se->icc_path); i++) {
>> +		icc_put(se->icc_path[i]);
> In geni_serial_icc_get() you hard open code this loop, so why not do the
> same here, to maintain some symmetry.
Ok
>
>> +		se->icc_path[i] = NULL;
> Again, what's the purpose of this clear?
Will remove this
>
>> +	}
>> +}
>> +
>>   static int qcom_geni_serial_request_port(struct uart_port *uport)
>>   {
>>   	struct platform_device *pdev = to_platform_device(uport->dev);
>> @@ -949,6 +978,12 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
>>   	ser_clk_cfg = SER_CLK_EN;
>>   	ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
>>   
>> +	/* Put BW vote only on CPU path as driver supports FIFO mode only */
>> +	port->se.avg_bw_cpu = Bps_to_icc(baud);
>> +	port->se.peak_bw_cpu = Bps_to_icc(2 * baud);
>> +	icc_set_bw(port->se.icc_path[CPU_TO_GENI], port->se.avg_bw_cpu,
>> +			port->se.peak_bw_cpu);
>> +
>>   	/* parity */
>>   	tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
>>   	tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
>> @@ -1179,11 +1214,20 @@ static void qcom_geni_serial_pm(struct uart_port *uport,
>>   	if (old_state == UART_PM_STATE_UNDEFINED)
>>   		old_state = UART_PM_STATE_OFF;
>>   
>> -	if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
>> +	if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
>> +		/* Put BW vote for core clocks and CPU */
>> +		icc_set_bw(port->se.icc_path[GENI_TO_CORE],
>> +			port->se.avg_bw_core, port->se.peak_bw_core);
>> +		icc_set_bw(port->se.icc_path[CPU_TO_GENI], port->se.avg_bw_cpu,
>> +			port->se.peak_bw_cpu);
>>   		geni_se_resources_on(&port->se);
>> -	else if (new_state == UART_PM_STATE_OFF &&
>> -			old_state == UART_PM_STATE_ON)
>> +	} else if (new_state == UART_PM_STATE_OFF &&
>> +			old_state == UART_PM_STATE_ON) {
>>   		geni_se_resources_off(&port->se);
>> +		/* Remove BW vote from core clocks and CPU */
>> +		icc_set_bw(port->se.icc_path[GENI_TO_CORE], 0, 0);
>> +		icc_set_bw(port->se.icc_path[CPU_TO_GENI], 0, 0);
>> +	}
>>   }
>>   
>>   static const struct uart_ops qcom_geni_console_pops = {
>> @@ -1274,15 +1318,30 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
>>   	port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
>>   	port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
>>   
>> +	ret = geni_serial_icc_get(&port->se);
>> +	if (ret)
>> +		return ret;
>> +	/* Set the bus quota to a reasonable value */
>> +	port->se.avg_bw_core = console ? Bps_to_icc(1000) :
>> +		Bps_to_icc(CORE_2X_50_MHZ);
>> +	port->se.peak_bw_core = console ? Bps_to_icc(1000) :
>> +		Bps_to_icc(CORE_2X_100_MHZ);
>> +	port->se.avg_bw_cpu = Bps_to_icc(1000);
>> +	port->se.avg_bw_cpu = Bps_to_icc(1000);
>> +
>>   	port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
>>   			"qcom_geni_serial_%s%d",
>>   			uart_console(uport) ? "console" : "uart", uport->line);
>> -	if (!port->name)
>> -		return -ENOMEM;
>> +	if (!port->name) {
>> +		ret = -ENOMEM;
>> +		goto geni_serial_put_icc;
> Rather than reworking the error handling like this, please introduce a
> devm_icc_get() function in the interconnect API.
>
> Regards,
> Bjorn

Ok will introduce devm_icc_get API.

Regards,

Akash

>> +	}
>>   
>>   	irq = platform_get_irq(pdev, 0);
>> -	if (irq < 0)
>> -		return irq;
>> +	if (irq < 0) {
>> +		ret = irq;
>> +		goto geni_serial_put_icc;
>> +	}
>>   	uport->irq = irq;
>>   	uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
>>   
>> @@ -1295,7 +1354,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
>>   
>>   	ret = uart_add_one_port(drv, uport);
>>   	if (ret)
>> -		return ret;
>> +		goto geni_serial_put_icc;
>>   
>>   	irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
>>   	ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
>> @@ -1303,7 +1362,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
>>   	if (ret) {
>>   		dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
>>   		uart_remove_one_port(drv, uport);
>> -		return ret;
>> +		goto geni_serial_put_icc;
>>   	}
>>   
>>   	/*
>> @@ -1320,11 +1379,15 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
>>   		if (ret) {
>>   			device_init_wakeup(&pdev->dev, false);
>>   			uart_remove_one_port(drv, uport);
>> -			return ret;
>> +			goto geni_serial_put_icc;
>>   		}
>>   	}
>>   
>>   	return 0;
>> +
>> +geni_serial_put_icc:
>> +	geni_serial_icc_put(&port->se);
>> +	return ret;
>>   }
>>   
>>   static int qcom_geni_serial_remove(struct platform_device *pdev)
>> @@ -1335,6 +1398,7 @@ static int qcom_geni_serial_remove(struct platform_device *pdev)
>>   	dev_pm_clear_wake_irq(&pdev->dev);
>>   	device_init_wakeup(&pdev->dev, false);
>>   	uart_remove_one_port(drv, &port->uport);
>> +	geni_serial_icc_put(&port->se);
>>   
>>   	return 0;
>>   }
>> -- 
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

Re: [PATCH 2/6] tty: serial: qcom_geni_serial: Add interconnect support

[Matthias Kaehlcke]

On Mon, Feb 17, 2020 at 07:00:01PM +0530, Akash Asthana wrote:
> Get the interconnect paths for Uart based Serial Engine device
> and vote according to the baud rate requirement of the driver.
> 
> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> ---
>  drivers/tty/serial/qcom_geni_serial.c | 84 ++++++++++++++++++++++++++++++-----
>  1 file changed, 74 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
> index 191abb1..a8fb2b7 100644
> --- a/drivers/tty/serial/qcom_geni_serial.c
> +++ b/drivers/tty/serial/qcom_geni_serial.c
> @@ -174,6 +174,35 @@ static struct qcom_geni_serial_port qcom_geni_console_port = {
>  	},
>  };
>  
> +static int geni_serial_icc_get(struct geni_se *se)
> +{
> +	if (!se)
> +		return -EINVAL;
> +
> +	se->icc_path[GENI_TO_CORE] = of_icc_get(se->dev, "qup-core");
> +	if (IS_ERR(se->icc_path[GENI_TO_CORE]))
> +		return PTR_ERR(se->icc_path[GENI_TO_CORE]);
> +
> +	se->icc_path[CPU_TO_GENI] = of_icc_get(se->dev, "qup-config");
> +	if (IS_ERR(se->icc_path[CPU_TO_GENI])) {
> +		icc_put(se->icc_path[GENI_TO_CORE]);
> +		se->icc_path[GENI_TO_CORE] = NULL;
> +		return PTR_ERR(se->icc_path[CPU_TO_GENI]);
> +	}
> +
> +	return 0;
> +}
> +
> +void geni_serial_icc_put(struct geni_se *se)
> +{
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(se->icc_path); i++) {
> +		icc_put(se->icc_path[i]);
> +		se->icc_path[i] = NULL;
> +	}
> +}
> +
>  static int qcom_geni_serial_request_port(struct uart_port *uport)
>  {
>  	struct platform_device *pdev = to_platform_device(uport->dev);
> @@ -949,6 +978,12 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
>  	ser_clk_cfg = SER_CLK_EN;
>  	ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
>  
> +	/* Put BW vote only on CPU path as driver supports FIFO mode only */
> +	port->se.avg_bw_cpu = Bps_to_icc(baud);
> +	port->se.peak_bw_cpu = Bps_to_icc(2 * baud);
> +	icc_set_bw(port->se.icc_path[CPU_TO_GENI], port->se.avg_bw_cpu,
> +			port->se.peak_bw_cpu);
> +
>  	/* parity */
>  	tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
>  	tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
> @@ -1179,11 +1214,20 @@ static void qcom_geni_serial_pm(struct uart_port *uport,
>  	if (old_state == UART_PM_STATE_UNDEFINED)
>  		old_state = UART_PM_STATE_OFF;
>  
> -	if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
> +	if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
> +		/* Put BW vote for core clocks and CPU */
> +		icc_set_bw(port->se.icc_path[GENI_TO_CORE],
> +			port->se.avg_bw_core, port->se.peak_bw_core);
> +		icc_set_bw(port->se.icc_path[CPU_TO_GENI], port->se.avg_bw_cpu,
> +			port->se.peak_bw_cpu);
>  		geni_se_resources_on(&port->se);
> -	else if (new_state == UART_PM_STATE_OFF &&
> -			old_state == UART_PM_STATE_ON)
> +	} else if (new_state == UART_PM_STATE_OFF &&
> +			old_state == UART_PM_STATE_ON) {
>  		geni_se_resources_off(&port->se);
> +		/* Remove BW vote from core clocks and CPU */
> +		icc_set_bw(port->se.icc_path[GENI_TO_CORE], 0, 0);
> +		icc_set_bw(port->se.icc_path[CPU_TO_GENI], 0, 0);
> +	}
>  }
>  
>  static const struct uart_ops qcom_geni_console_pops = {
> @@ -1274,15 +1318,30 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
>  	port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
>  	port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
>  
> +	ret = geni_serial_icc_get(&port->se);
> +	if (ret)
> +		return ret;
> +	/* Set the bus quota to a reasonable value */
> +	port->se.avg_bw_core = console ? Bps_to_icc(1000) :
> +		Bps_to_icc(CORE_2X_50_MHZ);
> +	port->se.peak_bw_core = console ? Bps_to_icc(1000) :
> +		Bps_to_icc(CORE_2X_100_MHZ);
> +	port->se.avg_bw_cpu = Bps_to_icc(1000);
> +	port->se.avg_bw_cpu = Bps_to_icc(1000);

I guess you mean 'peak_bw_cpu'?

Re: [PATCH 2/6] tty: serial: qcom_geni_serial: Add interconnect support

[Akash Asthana]

Hi Matthias,

On 2/19/2020 4:04 AM, Matthias Kaehlcke wrote:
> On Mon, Feb 17, 2020 at 07:00:01PM +0530, Akash Asthana wrote:
>> Get the interconnect paths for Uart based Serial Engine device
>> and vote according to the baud rate requirement of the driver.
>>
>> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
>> ---
>>
>> +	port->se.avg_bw_cpu = Bps_to_icc(1000);
>> +	port->se.avg_bw_cpu = Bps_to_icc(1000);
> I guess you mean 'peak_bw_cpu'?

Yes I meant peak_bw_cpu here, i will correct it in next version.

Regards,

Akash

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

[PATCH 3/6] i2c: i2c-qcom-geni: Add interconnect support

[Akash Asthana]

Get the interconnect paths for I2C based Serial Engine device
and vote according to the bus speed of the driver.

Signed-off-by: Akash Asthana <akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 drivers/i2c/busses/i2c-qcom-geni.c | 84 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 80 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index 17abf60c..5de10a1 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -163,6 +163,44 @@ static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
 	writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
 }
 
+static int geni_i2c_icc_get(struct geni_se *se)
+{
+	if (!se)
+		return -EINVAL;
+
+	se->icc_path[GENI_TO_CORE] = of_icc_get(se->dev, "qup-core");
+	if (IS_ERR(se->icc_path[GENI_TO_CORE]))
+		return PTR_ERR(se->icc_path[GENI_TO_CORE]);
+
+	se->icc_path[CPU_TO_GENI] = of_icc_get(se->dev, "qup-config");
+	if (IS_ERR(se->icc_path[CPU_TO_GENI])) {
+		icc_put(se->icc_path[GENI_TO_CORE]);
+		se->icc_path[GENI_TO_CORE] = NULL;
+		return PTR_ERR(se->icc_path[CPU_TO_GENI]);
+	}
+
+	se->icc_path[GENI_TO_DDR] = of_icc_get(se->dev, "qup-memory");
+	if (IS_ERR(se->icc_path[GENI_TO_DDR])) {
+		icc_put(se->icc_path[GENI_TO_CORE]);
+		se->icc_path[GENI_TO_CORE] = NULL;
+		icc_put(se->icc_path[CPU_TO_GENI]);
+		se->icc_path[CPU_TO_GENI] = NULL;
+		return PTR_ERR(se->icc_path[GENI_TO_DDR]);
+	}
+
+	return 0;
+}
+
+void geni_i2c_icc_put(struct geni_se *se)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(se->icc_path); i++) {
+		icc_put(se->icc_path[i]);
+		se->icc_path[i] = NULL;
+	}
+}
+
 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
 {
 	u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
@@ -563,17 +601,34 @@ static int geni_i2c_probe(struct platform_device *pdev)
 	gi2c->adap.dev.of_node = pdev->dev.of_node;
 	strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
 
+	ret = geni_i2c_icc_get(&gi2c->se);
+	if (ret)
+		return ret;
+	/* Set the bus quota to a reasonable value */
+	gi2c->se.avg_bw_core = Bps_to_icc(1000);
+	gi2c->se.peak_bw_core = Bps_to_icc(CORE_2X_100_MHZ);
+	gi2c->se.avg_bw_cpu = Bps_to_icc(1000);
+	gi2c->se.peak_bw_cpu = Bps_to_icc(1000);
+	gi2c->se.avg_bw_ddr = Bps_to_icc(gi2c->clk_freq_out);
+	gi2c->se.peak_bw_ddr = Bps_to_icc(2 * gi2c->clk_freq_out);
+
+	/* Vote for core clocks and CPU for register access */
+	icc_set_bw(gi2c->se.icc_path[GENI_TO_CORE], gi2c->se.avg_bw_core,
+				gi2c->se.peak_bw_core);
+	icc_set_bw(gi2c->se.icc_path[CPU_TO_GENI], gi2c->se.avg_bw_cpu,
+				gi2c->se.peak_bw_cpu);
 	ret = geni_se_resources_on(&gi2c->se);
 	if (ret) {
 		dev_err(&pdev->dev, "Error turning on resources %d\n", ret);
-		return ret;
+		goto geni_i2c_put_icc;
 	}
 	proto = geni_se_read_proto(&gi2c->se);
 	tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
 	if (proto != GENI_SE_I2C) {
 		dev_err(&pdev->dev, "Invalid proto %d\n", proto);
 		geni_se_resources_off(&gi2c->se);
-		return -ENXIO;
+		ret = -ENXIO;
+		goto geni_i2c_put_icc;
 	}
 	gi2c->tx_wm = tx_depth - 1;
 	geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
@@ -582,8 +637,11 @@ static int geni_i2c_probe(struct platform_device *pdev)
 	ret = geni_se_resources_off(&gi2c->se);
 	if (ret) {
 		dev_err(&pdev->dev, "Error turning off resources %d\n", ret);
-		return ret;
+		goto geni_i2c_put_icc;
 	}
+	/* Remove vote from core clocks and CPU */
+	icc_set_bw(gi2c->se.icc_path[GENI_TO_CORE], 0, 0);
+	icc_set_bw(gi2c->se.icc_path[CPU_TO_GENI], 0, 0);
 
 	dev_dbg(&pdev->dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
 
@@ -597,12 +655,16 @@ static int geni_i2c_probe(struct platform_device *pdev)
 	if (ret) {
 		dev_err(&pdev->dev, "Error adding i2c adapter %d\n", ret);
 		pm_runtime_disable(gi2c->se.dev);
-		return ret;
+		goto geni_i2c_put_icc;
 	}
 
 	dev_dbg(&pdev->dev, "Geni-I2C adaptor successfully added\n");
 
 	return 0;
+
+geni_i2c_put_icc:
+	geni_i2c_icc_put(&gi2c->se);
+	return ret;
 }
 
 static int geni_i2c_remove(struct platform_device *pdev)
@@ -611,6 +673,7 @@ static int geni_i2c_remove(struct platform_device *pdev)
 
 	i2c_del_adapter(&gi2c->adap);
 	pm_runtime_disable(gi2c->se.dev);
+	geni_i2c_icc_put(&gi2c->se);
 	return 0;
 }
 
@@ -629,6 +692,11 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
 		gi2c->suspended = 1;
 	}
 
+	/* Remove BW votes */
+	icc_set_bw(gi2c->se.icc_path[GENI_TO_CORE], 0, 0);
+	icc_set_bw(gi2c->se.icc_path[CPU_TO_GENI], 0, 0);
+	icc_set_bw(gi2c->se.icc_path[GENI_TO_DDR], 0, 0);
+
 	return 0;
 }
 
@@ -637,6 +705,14 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
 	int ret;
 	struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
 
+	/* Vote on Core, DDR and CPU path respectively */
+	icc_set_bw(gi2c->se.icc_path[GENI_TO_CORE], gi2c->se.avg_bw_core,
+		gi2c->se.peak_bw_core);
+	icc_set_bw(gi2c->se.icc_path[CPU_TO_GENI], gi2c->se.avg_bw_cpu,
+		gi2c->se.peak_bw_cpu);
+	icc_set_bw(gi2c->se.icc_path[GENI_TO_DDR], gi2c->se.avg_bw_ddr,
+		gi2c->se.peak_bw_ddr);
+
 	ret = geni_se_resources_on(&gi2c->se);
 	if (ret)
 		return ret;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

Re: [PATCH 3/6] i2c: i2c-qcom-geni: Add interconnect support

[Matthias Kaehlcke]

On Mon, Feb 17, 2020 at 07:00:02PM +0530, Akash Asthana wrote:
> Get the interconnect paths for I2C based Serial Engine device
> and vote according to the bus speed of the driver.
> 
> Signed-off-by: Akash Asthana <akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>  drivers/i2c/busses/i2c-qcom-geni.c | 84 ++++++++++++++++++++++++++++++++++++--
>  1 file changed, 80 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
> index 17abf60c..5de10a1 100644
> --- a/drivers/i2c/busses/i2c-qcom-geni.c
> +++ b/drivers/i2c/busses/i2c-qcom-geni.c
> @@ -163,6 +163,44 @@ static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
>  	writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
>  }
>  
> +static int geni_i2c_icc_get(struct geni_se *se)
> +{
> +	if (!se)
> +		return -EINVAL;

check is not needed

> +
> +	se->icc_path[GENI_TO_CORE] = of_icc_get(se->dev, "qup-core");
> +	if (IS_ERR(se->icc_path[GENI_TO_CORE]))
> +		return PTR_ERR(se->icc_path[GENI_TO_CORE]);
> +
> +	se->icc_path[CPU_TO_GENI] = of_icc_get(se->dev, "qup-config");
> +	if (IS_ERR(se->icc_path[CPU_TO_GENI])) {
> +		icc_put(se->icc_path[GENI_TO_CORE]);
> +		se->icc_path[GENI_TO_CORE] = NULL;

echoing Bjorn's comments on 'tty: serial: qcom_geni_serial: Add
interconnect support', resetting is not needed since _probe() will
fail.

> +		return PTR_ERR(se->icc_path[CPU_TO_GENI]);
> +	}
> +
> +	se->icc_path[GENI_TO_DDR] = of_icc_get(se->dev, "qup-memory");
> +	if (IS_ERR(se->icc_path[GENI_TO_DDR])) {
> +		icc_put(se->icc_path[GENI_TO_CORE]);
> +		se->icc_path[GENI_TO_CORE] = NULL;

ditto

> +		icc_put(se->icc_path[CPU_TO_GENI]);
> +		se->icc_path[CPU_TO_GENI] = NULL;

ditto

> +		return PTR_ERR(se->icc_path[GENI_TO_DDR]);
> +	}
> +
> +	return 0;
> +}
> +
> +void geni_i2c_icc_put(struct geni_se *se)
> +{
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(se->icc_path); i++) {
> +		icc_put(se->icc_path[i]);
> +		se->icc_path[i] = NULL;

not needed

> +	}
> +}
> +
>  static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
>  {
>  	u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
> @@ -563,17 +601,34 @@ static int geni_i2c_probe(struct platform_device *pdev)
>  	gi2c->adap.dev.of_node = pdev->dev.of_node;
>  	strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
>  
> +	ret = geni_i2c_icc_get(&gi2c->se);
> +	if (ret)
> +		return ret;
> +	/* Set the bus quota to a reasonable value */
> +	gi2c->se.avg_bw_core = Bps_to_icc(1000);
> +	gi2c->se.peak_bw_core = Bps_to_icc(CORE_2X_100_MHZ);
> +	gi2c->se.avg_bw_cpu = Bps_to_icc(1000);
> +	gi2c->se.peak_bw_cpu = Bps_to_icc(1000);
> +	gi2c->se.avg_bw_ddr = Bps_to_icc(gi2c->clk_freq_out);
> +	gi2c->se.peak_bw_ddr = Bps_to_icc(2 * gi2c->clk_freq_out);
> +
> +	/* Vote for core clocks and CPU for register access */
> +	icc_set_bw(gi2c->se.icc_path[GENI_TO_CORE], gi2c->se.avg_bw_core,
> +				gi2c->se.peak_bw_core);
> +	icc_set_bw(gi2c->se.icc_path[CPU_TO_GENI], gi2c->se.avg_bw_cpu,
> +				gi2c->se.peak_bw_cpu);

error handling needed?

Re: [PATCH 3/6] i2c: i2c-qcom-geni: Add interconnect support

[Akash Asthana]

Hi Matthias,

On 2/19/2020 4:17 AM, Matthias Kaehlcke wrote:
> On Mon, Feb 17, 2020 at 07:00:02PM +0530, Akash Asthana wrote:
>> Get the interconnect paths for I2C based Serial Engine device
>> and vote according to the bus speed of the driver.
>>
>> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
>> ---
>>   drivers/i2c/busses/i2c-qcom-geni.c | 84 ++++++++++++++++++++++++++++++++++++--
>>   1 file changed, 80 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
>> index 17abf60c..5de10a1 100644
>> --- a/drivers/i2c/busses/i2c-qcom-geni.c
>> +++ b/drivers/i2c/busses/i2c-qcom-geni.c
>> @@ -163,6 +163,44 @@ static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
>>   	writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
>>   }
>>   
>> +static int geni_i2c_icc_get(struct geni_se *se)
>> +{
>> +	if (!se)
>> +		return -EINVAL;
> check is not needed
ok, will remove.
>
>> +
>> +	se->icc_path[GENI_TO_CORE] = of_icc_get(se->dev, "qup-core");
>> +	if (IS_ERR(se->icc_path[GENI_TO_CORE]))
>> +		return PTR_ERR(se->icc_path[GENI_TO_CORE]);
>> +
>> +	se->icc_path[CPU_TO_GENI] = of_icc_get(se->dev, "qup-config");
>> +	if (IS_ERR(se->icc_path[CPU_TO_GENI])) {
>> +		icc_put(se->icc_path[GENI_TO_CORE]);
>> +		se->icc_path[GENI_TO_CORE] = NULL;
> echoing Bjorn's comments on 'tty: serial: qcom_geni_serial: Add
> interconnect support', resetting is not needed since _probe() will
> fail.
ok, will remove
>> +		return PTR_ERR(se->icc_path[CPU_TO_GENI]);
>> +	}
>> +
>> +	se->icc_path[GENI_TO_DDR] = of_icc_get(se->dev, "qup-memory");
>> +	if (IS_ERR(se->icc_path[GENI_TO_DDR])) {
>> +		icc_put(se->icc_path[GENI_TO_CORE]);
>> +		se->icc_path[GENI_TO_CORE] = NULL;
> ditto
ok
>> +		icc_put(se->icc_path[CPU_TO_GENI]);
>> +		se->icc_path[CPU_TO_GENI] = NULL;
> ditto
ok
>> +		return PTR_ERR(se->icc_path[GENI_TO_DDR]);
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +void geni_i2c_icc_put(struct geni_se *se)
>> +{
>> +	int i;
>> +
>> +	for (i = 0; i < ARRAY_SIZE(se->icc_path); i++) {
>> +		icc_put(se->icc_path[i]);
>> +		se->icc_path[i] = NULL;
> not needed
ok, will remove
>> +	}
>> +}
>> +
>>   static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
>>   {
>>   	u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
>> @@ -563,17 +601,34 @@ static int geni_i2c_probe(struct platform_device *pdev)
>>   	gi2c->adap.dev.of_node = pdev->dev.of_node;
>>   	strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
>>   
>> +	ret = geni_i2c_icc_get(&gi2c->se);
>> +	if (ret)
>> +		return ret;
>> +	/* Set the bus quota to a reasonable value */
>> +	gi2c->se.avg_bw_core = Bps_to_icc(1000);
>> +	gi2c->se.peak_bw_core = Bps_to_icc(CORE_2X_100_MHZ);
>> +	gi2c->se.avg_bw_cpu = Bps_to_icc(1000);
>> +	gi2c->se.peak_bw_cpu = Bps_to_icc(1000);
>> +	gi2c->se.avg_bw_ddr = Bps_to_icc(gi2c->clk_freq_out);
>> +	gi2c->se.peak_bw_ddr = Bps_to_icc(2 * gi2c->clk_freq_out);
>> +
>> +	/* Vote for core clocks and CPU for register access */
>> +	icc_set_bw(gi2c->se.icc_path[GENI_TO_CORE], gi2c->se.avg_bw_core,
>> +				gi2c->se.peak_bw_core);
>> +	icc_set_bw(gi2c->se.icc_path[CPU_TO_GENI], gi2c->se.avg_bw_cpu,
>> +				gi2c->se.peak_bw_cpu);
> error handling needed?

I will add error handling for GENI_TO_CORE path in all the drivers. Will 
it be okay if we don't handle errors for CPU_TO_GENI and GENI_TO_DDR path

as CPU and DDR will be running at much higher frequency?

Regards,

Akash

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

Re: [PATCH 3/6] i2c: i2c-qcom-geni: Add interconnect support

[Matthias Kaehlcke]

Hi Akash,

On Wed, Feb 19, 2020 at 07:17:44PM +0530, Akash Asthana wrote:
> Hi Matthias,
> 
> On 2/19/2020 4:17 AM, Matthias Kaehlcke wrote:
> > On Mon, Feb 17, 2020 at 07:00:02PM +0530, Akash Asthana wrote:
> > > Get the interconnect paths for I2C based Serial Engine device
> > > and vote according to the bus speed of the driver.
> > > 
> > > Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> > > ---
> > >   drivers/i2c/busses/i2c-qcom-geni.c | 84 ++++++++++++++++++++++++++++++++++++--
> > >   1 file changed, 80 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
> > > index 17abf60c..5de10a1 100644
> > > --- a/drivers/i2c/busses/i2c-qcom-geni.c
> > > +++ b/drivers/i2c/busses/i2c-qcom-geni.c
> > >
> > >   static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
> > >   {
> > >   	u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
> > > @@ -563,17 +601,34 @@ static int geni_i2c_probe(struct platform_device *pdev)
> > >   	gi2c->adap.dev.of_node = pdev->dev.of_node;
> > >   	strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
> > > +	ret = geni_i2c_icc_get(&gi2c->se);
> > > +	if (ret)
> > > +		return ret;
> > > +	/* Set the bus quota to a reasonable value */
> > > +	gi2c->se.avg_bw_core = Bps_to_icc(1000);
> > > +	gi2c->se.peak_bw_core = Bps_to_icc(CORE_2X_100_MHZ);
> > > +	gi2c->se.avg_bw_cpu = Bps_to_icc(1000);
> > > +	gi2c->se.peak_bw_cpu = Bps_to_icc(1000);
> > > +	gi2c->se.avg_bw_ddr = Bps_to_icc(gi2c->clk_freq_out);
> > > +	gi2c->se.peak_bw_ddr = Bps_to_icc(2 * gi2c->clk_freq_out);
> > > +
> > > +	/* Vote for core clocks and CPU for register access */
> > > +	icc_set_bw(gi2c->se.icc_path[GENI_TO_CORE], gi2c->se.avg_bw_core,
> > > +				gi2c->se.peak_bw_core);
> > > +	icc_set_bw(gi2c->se.icc_path[CPU_TO_GENI], gi2c->se.avg_bw_cpu,
> > > +				gi2c->se.peak_bw_cpu);
> > error handling needed?
> 
> I will add error handling for GENI_TO_CORE path in all the drivers. Will it
> be okay if we don't handle errors for CPU_TO_GENI and GENI_TO_DDR path
> 
> as CPU and DDR will be running at much higher frequency?

It may still work, but you might never know that there was a problem. I
would be inclined to check the return value of all invocations of icc_set_bw()
- including runtime suspend/resume - and log a message if a problem is
detected. For runtime suspend/resume it would probably be wise to use
dev_err_ratelimited(), to avoid spamming the system log too much in case of
a persistent problem.

If others think that error checking all icc_set_bw() calls is overkill
please speak up :)

Thanks

Matthias

Re: [PATCH 0/6] Add interconnect support to UART, I2C, SPI and QSPI

[Matthias Kaehlcke]

Hi Akash,

do you plan to re-spin this series in the near future?

Thanks

Matthias

On Mon, Feb 17, 2020 at 06:59:59PM +0530, Akash Asthana wrote:
> dt-binding patch for UART, I2C and SPI.
>  - https://patchwork.kernel.org/patch/11385965/ [Convert QUP bindings
> 	to YAML and add ICC, pin swap doc]
> 
> dt-binding patch for QSPI.
>  - https://patchwork.kernel.org/cover/11386003/ [Convert QSPI binding
> 	to YAML and add interconnect doc]
> 
> Akash Asthana (6):
>   soc: qcom: geni: Support for ICC voting
>   tty: serial: qcom_geni_serial: Add interconnect support
>   i2c: i2c-qcom-geni: Add interconnect support
>   spi: spi-geni-qcom: Add interconnect support
>   spi: spi-qcom-qspi: Add interconnect support
>   arm64: dts: sc7180: Add interconnect for QUP and QSPI
> 
>  arch/arm64/boot/dts/qcom/sc7180.dtsi  | 199 ++++++++++++++++++++++++++++++++++
>  drivers/i2c/busses/i2c-qcom-geni.c    |  84 +++++++++++++-
>  drivers/spi/spi-geni-qcom.c           |  65 ++++++++++-
>  drivers/spi/spi-qcom-qspi.c           |  38 ++++++-
>  drivers/tty/serial/qcom_geni_serial.c |  84 ++++++++++++--
>  include/linux/qcom-geni-se.h          |  31 ++++++
>  6 files changed, 481 insertions(+), 20 deletions(-)
> 
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

Re: [PATCH 0/6] Add interconnect support to UART, I2C, SPI and QSPI

[Akash Asthana]

On 3/9/2020 11:29 PM, Matthias Kaehlcke wrote:
> Hi Akash,
>
> do you plan to re-spin this series in the near future?
>
> Thanks
>
> Matthias

Hi  Matthias,

I will re-spin the series by 3/13.

Regards,

Akash

>
> On Mon, Feb 17, 2020 at 06:59:59PM +0530, Akash Asthana wrote:
>> dt-binding patch for UART, I2C and SPI.
>>   - https://patchwork.kernel.org/patch/11385965/ [Convert QUP bindings
>> 	to YAML and add ICC, pin swap doc]
>>
>> dt-binding patch for QSPI.
>>   - https://patchwork.kernel.org/cover/11386003/ [Convert QSPI binding
>> 	to YAML and add interconnect doc]
>>
>> Akash Asthana (6):
>>    soc: qcom: geni: Support for ICC voting
>>    tty: serial: qcom_geni_serial: Add interconnect support
>>    i2c: i2c-qcom-geni: Add interconnect support
>>    spi: spi-geni-qcom: Add interconnect support
>>    spi: spi-qcom-qspi: Add interconnect support
>>    arm64: dts: sc7180: Add interconnect for QUP and QSPI
>>
>>   arch/arm64/boot/dts/qcom/sc7180.dtsi  | 199 ++++++++++++++++++++++++++++++++++
>>   drivers/i2c/busses/i2c-qcom-geni.c    |  84 +++++++++++++-
>>   drivers/spi/spi-geni-qcom.c           |  65 ++++++++++-
>>   drivers/spi/spi-qcom-qspi.c           |  38 ++++++-
>>   drivers/tty/serial/qcom_geni_serial.c |  84 ++++++++++++--
>>   include/linux/qcom-geni-se.h          |  31 ++++++
>>   6 files changed, 481 insertions(+), 20 deletions(-)
>>
>> -- 
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

[PATCH 4/6] spi: spi-geni-qcom: Add interconnect support

[Akash Asthana]

Get the interconnect paths for SPI based Serial Engine device
and vote according to the current bus speed of the driver.

Signed-off-by: Akash Asthana <akashast@codeaurora.org>
---
 drivers/spi/spi-geni-qcom.c | 65 ++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 62 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index c397242..a066ef26 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -118,6 +118,35 @@ static int get_spi_clk_cfg(unsigned int speed_hz,
 	return ret;
 }
 
+static int geni_spi_icc_get(struct geni_se *se)
+{
+	if (!se)
+		return -EINVAL;
+
+	se->icc_path[GENI_TO_CORE] = of_icc_get(se->dev, "qup-core");
+	if (IS_ERR(se->icc_path[GENI_TO_CORE]))
+		return PTR_ERR(se->icc_path[GENI_TO_CORE]);
+
+	se->icc_path[CPU_TO_GENI] = of_icc_get(se->dev, "qup-config");
+	if (IS_ERR(se->icc_path[CPU_TO_GENI])) {
+		icc_put(se->icc_path[GENI_TO_CORE]);
+		se->icc_path[GENI_TO_CORE] = NULL;
+		return PTR_ERR(se->icc_path[CPU_TO_GENI]);
+	}
+
+	return 0;
+}
+
+void geni_spi_icc_put(struct geni_se *se)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(se->icc_path); i++) {
+		icc_put(se->icc_path[i]);
+		se->icc_path[i] = NULL;
+	}
+}
+
 static void handle_fifo_timeout(struct spi_master *spi,
 				struct spi_message *msg)
 {
@@ -234,6 +263,11 @@ static int setup_fifo_params(struct spi_device *spi_slv,
 		return ret;
 	}
 
+	/* Set BW quota for CPU as driver supports FIFO mode only */
+	se->avg_bw_cpu = Bps_to_icc(mas->cur_speed_hz);
+	se->peak_bw_cpu = Bps_to_icc(2 * mas->cur_speed_hz);
+	icc_set_bw(se->icc_path[CPU_TO_GENI], se->avg_bw_cpu, se->peak_bw_cpu);
+
 	clk_sel = idx & CLK_SEL_MSK;
 	m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
 	spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
@@ -578,13 +612,22 @@ static int spi_geni_probe(struct platform_device *pdev)
 	spin_lock_init(&mas->lock);
 	pm_runtime_enable(dev);
 
-	ret = spi_geni_init(mas);
+	ret = geni_spi_icc_get(&mas->se);
 	if (ret)
 		goto spi_geni_probe_runtime_disable;
+	/* Set the bus quota to a reasonable value */
+	mas->se.avg_bw_core = Bps_to_icc(CORE_2X_50_MHZ);
+	mas->se.peak_bw_core = Bps_to_icc(CORE_2X_100_MHZ);
+	mas->se.avg_bw_cpu = Bps_to_icc(1000);
+	mas->se.peak_bw_cpu = Bps_to_icc(1000);
+
+	ret = spi_geni_init(mas);
+	if (ret)
+		goto spi_geni_icc_put;
 
 	ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
 	if (ret)
-		goto spi_geni_probe_runtime_disable;
+		goto spi_geni_icc_put;
 
 	ret = spi_register_master(spi);
 	if (ret)
@@ -593,6 +636,8 @@ static int spi_geni_probe(struct platform_device *pdev)
 	return 0;
 spi_geni_probe_free_irq:
 	free_irq(mas->irq, spi);
+spi_geni_icc_put:
+	geni_spi_icc_put(&mas->se);
 spi_geni_probe_runtime_disable:
 	pm_runtime_disable(dev);
 	spi_master_put(spi);
@@ -608,16 +653,25 @@ static int spi_geni_remove(struct platform_device *pdev)
 	spi_unregister_master(spi);
 
 	free_irq(mas->irq, spi);
+	geni_spi_icc_put(&mas->se);
 	pm_runtime_disable(&pdev->dev);
 	return 0;
 }
 
 static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
 {
+	int ret;
 	struct spi_master *spi = dev_get_drvdata(dev);
 	struct spi_geni_master *mas = spi_master_get_devdata(spi);
 
-	return geni_se_resources_off(&mas->se);
+	ret = geni_se_resources_off(&mas->se);
+	if (ret)
+		return ret;
+
+	icc_set_bw(mas->se.icc_path[GENI_TO_CORE], 0, 0);
+	icc_set_bw(mas->se.icc_path[CPU_TO_GENI], 0, 0);
+
+	return 0;
 }
 
 static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
@@ -625,6 +679,11 @@ static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
 	struct spi_master *spi = dev_get_drvdata(dev);
 	struct spi_geni_master *mas = spi_master_get_devdata(spi);
 
+	icc_set_bw(mas->se.icc_path[GENI_TO_CORE], mas->se.avg_bw_core,
+		mas->se.peak_bw_core);
+	icc_set_bw(mas->se.icc_path[CPU_TO_GENI], mas->se.avg_bw_cpu,
+		mas->se.peak_bw_cpu);
+
 	return geni_se_resources_on(&mas->se);
 }
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

Re: [PATCH 4/6] spi: spi-geni-qcom: Add interconnect support

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 260 bytes --]

On Mon, Feb 17, 2020 at 07:00:03PM +0530, Akash Asthana wrote:
> Get the interconnect paths for SPI based Serial Engine device
> and vote according to the current bus speed of the driver.

Acked-by: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [PATCH 4/6] spi: spi-geni-qcom: Add interconnect support

[Matthias Kaehlcke]

On Mon, Feb 17, 2020 at 07:00:03PM +0530, Akash Asthana wrote:
> Get the interconnect paths for SPI based Serial Engine device
> and vote according to the current bus speed of the driver.
> 
> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> ---
>  drivers/spi/spi-geni-qcom.c | 65 ++++++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 62 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
> index c397242..a066ef26 100644
> --- a/drivers/spi/spi-geni-qcom.c
> +++ b/drivers/spi/spi-geni-qcom.c
> @@ -608,16 +653,25 @@ static int spi_geni_remove(struct platform_device *pdev)
>  	spi_unregister_master(spi);
>  
>  	free_irq(mas->irq, spi);
> +	geni_spi_icc_put(&mas->se);
>  	pm_runtime_disable(&pdev->dev);
>  	return 0;
>  }
>  
>  static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
>  {
> +	int ret;
>  	struct spi_master *spi = dev_get_drvdata(dev);
>  	struct spi_geni_master *mas = spi_master_get_devdata(spi);
>  
> -	return geni_se_resources_off(&mas->se);
> +	ret = geni_se_resources_off(&mas->se);
> +	if (ret)
> +		return ret;
> +
> +	icc_set_bw(mas->se.icc_path[GENI_TO_CORE], 0, 0);

This causes my SC7180 system to reset at boot time:

[    3.509652] qcom-qmp-phy 88e9000.phy-wrapper: Registered Qcom-QMP phy
[    3.516956] qcom-qusb2-phy 88e3000.phy: Registered Qcom-QUSB2 phy
[    3.524450] geni_se_qup 8c0000.geniqup: Adding to iommu group 4
[    3.533896] spi_master spi0: will run message pump with realtime priority
<reset>

The system does not reset when passing 'Bps_to_icc(1000)' (=> 1) instead of 0.

Re: [PATCH 4/6] spi: spi-geni-qcom: Add interconnect support

[Matthias Kaehlcke]

On Wed, Feb 19, 2020 at 10:09:50AM -0800, Matthias Kaehlcke wrote:
> On Mon, Feb 17, 2020 at 07:00:03PM +0530, Akash Asthana wrote:
> > Get the interconnect paths for SPI based Serial Engine device
> > and vote according to the current bus speed of the driver.
> > 
> > Signed-off-by: Akash Asthana <akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> > ---
> >  drivers/spi/spi-geni-qcom.c | 65 ++++++++++++++++++++++++++++++++++++++++++---
> >  1 file changed, 62 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
> > index c397242..a066ef26 100644
> > --- a/drivers/spi/spi-geni-qcom.c
> > +++ b/drivers/spi/spi-geni-qcom.c
> > @@ -608,16 +653,25 @@ static int spi_geni_remove(struct platform_device *pdev)
> >  	spi_unregister_master(spi);
> >  
> >  	free_irq(mas->irq, spi);
> > +	geni_spi_icc_put(&mas->se);
> >  	pm_runtime_disable(&pdev->dev);
> >  	return 0;
> >  }
> >  
> >  static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
> >  {
> > +	int ret;
> >  	struct spi_master *spi = dev_get_drvdata(dev);
> >  	struct spi_geni_master *mas = spi_master_get_devdata(spi);
> >  
> > -	return geni_se_resources_off(&mas->se);
> > +	ret = geni_se_resources_off(&mas->se);
> > +	if (ret)
> > +		return ret;
> > +
> > +	icc_set_bw(mas->se.icc_path[GENI_TO_CORE], 0, 0);
> 
> This causes my SC7180 system to reset at boot time:
> 
> [    3.509652] qcom-qmp-phy 88e9000.phy-wrapper: Registered Qcom-QMP phy
> [    3.516956] qcom-qusb2-phy 88e3000.phy: Registered Qcom-QUSB2 phy
> [    3.524450] geni_se_qup 8c0000.geniqup: Adding to iommu group 4
> [    3.533896] spi_master spi0: will run message pump with realtime priority
> <reset>
> 
> The system does not reset when passing 'Bps_to_icc(1000)' (=> 1) instead of 0.

I found this is related with the use of 'earlycon'.

There is a short window where the early console and the 'real' console coexist:

[    3.858122] printk: console [ttyMSM0] enabled
[    3.875692] printk: bootconsole [qcom_geni0] disabled

The reset probably occurs when the early console tries to write, but the ICC is
effectively disabled because ttyMSM0 and the other geni ports are runtime
suspended.

In any case that's not an issue of the SPI driver, but needs to be addressed
somewhere in the console/UART code.

[PATCH 5/6] spi: spi-qcom-qspi: Add interconnect support

[Akash Asthana]

Get the interconnect paths for QSPI device and vote according to the
current bus speed of the driver.

Signed-off-by: Akash Asthana <akashast@codeaurora.org>
---
 drivers/spi/spi-qcom-qspi.c | 38 +++++++++++++++++++++++++++++++++++---
 1 file changed, 35 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c
index 3c4f83b..3636438 100644
--- a/drivers/spi/spi-qcom-qspi.c
+++ b/drivers/spi/spi-qcom-qspi.c
@@ -2,6 +2,7 @@
 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
 
 #include <linux/clk.h>
+#include <linux/interconnect.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/module.h>
@@ -134,12 +135,19 @@ enum qspi_clocks {
 	QSPI_NUM_CLKS
 };
 
+enum qspi_icc_path {
+	CPU_TO_QSPI
+};
+
 struct qcom_qspi {
 	void __iomem *base;
 	struct device *dev;
 	struct clk_bulk_data *clks;
 	struct qspi_xfer xfer;
-	/* Lock to protect xfer and IRQ accessed registers */
+	struct icc_path *icc_path[2];
+	unsigned int avg_bw_cpu;
+	unsigned int peak_bw_cpu;
+	/* Lock to protect data accessed by IRQs */
 	spinlock_t lock;
 };
 
@@ -241,6 +249,11 @@ static int qcom_qspi_transfer_one(struct spi_master *master,
 		return ret;
 	}
 
+	/* Set BW quota for CPU as driver supports FIFO mode only */
+	ctrl->avg_bw_cpu = Bps_to_icc(speed_hz);
+	ctrl->peak_bw_cpu = Bps_to_icc(2 * speed_hz);
+	icc_set_bw(ctrl->icc_path[CPU_TO_QSPI], ctrl->avg_bw_cpu, ctrl->peak_bw_cpu);
+
 	spin_lock_irqsave(&ctrl->lock, flags);
 
 	/* We are half duplex, so either rx or tx will be set */
@@ -458,14 +471,23 @@ static int qcom_qspi_probe(struct platform_device *pdev)
 	if (ret)
 		goto exit_probe_master_put;
 
+	ctrl->icc_path[CPU_TO_QSPI] = of_icc_get(dev, "qspi-config");
+	if (IS_ERR(ctrl->icc_path[CPU_TO_QSPI])) {
+		ret = PTR_ERR(ctrl->icc_path[CPU_TO_QSPI]);
+		goto exit_probe_master_put;
+	}
+	/* Put BW vote on CPU path for register access */
+	ctrl->avg_bw_cpu = Bps_to_icc(1000);
+	ctrl->peak_bw_cpu = Bps_to_icc(1000);
+
 	ret = platform_get_irq(pdev, 0);
 	if (ret < 0)
-		goto exit_probe_master_put;
+		goto exit_probe_icc_put;
 	ret = devm_request_irq(dev, ret, qcom_qspi_irq,
 			IRQF_TRIGGER_HIGH, dev_name(dev), ctrl);
 	if (ret) {
 		dev_err(dev, "Failed to request irq %d\n", ret);
-		goto exit_probe_master_put;
+		goto exit_probe_icc_put;
 	}
 
 	master->max_speed_hz = 300000000;
@@ -489,6 +511,8 @@ static int qcom_qspi_probe(struct platform_device *pdev)
 
 	pm_runtime_disable(dev);
 
+exit_probe_icc_put:
+	icc_put(ctrl->icc_path[CPU_TO_QSPI]);
 exit_probe_master_put:
 	spi_master_put(master);
 
@@ -498,6 +522,9 @@ static int qcom_qspi_probe(struct platform_device *pdev)
 static int qcom_qspi_remove(struct platform_device *pdev)
 {
 	struct spi_master *master = platform_get_drvdata(pdev);
+	struct qcom_qspi *ctrl = spi_master_get_devdata(master);
+
+	icc_put(ctrl->icc_path[CPU_TO_QSPI]);
 
 	/* Unregister _before_ disabling pm_runtime() so we stop transfers */
 	spi_unregister_master(master);
@@ -514,6 +541,8 @@ static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev)
 
 	clk_bulk_disable_unprepare(QSPI_NUM_CLKS, ctrl->clks);
 
+	icc_set_bw(ctrl->icc_path[CPU_TO_QSPI], 0, 0);
+
 	return 0;
 }
 
@@ -522,6 +551,9 @@ static int __maybe_unused qcom_qspi_runtime_resume(struct device *dev)
 	struct spi_master *master = dev_get_drvdata(dev);
 	struct qcom_qspi *ctrl = spi_master_get_devdata(master);
 
+	icc_set_bw(ctrl->icc_path[CPU_TO_QSPI], ctrl->avg_bw_cpu,
+		ctrl->peak_bw_cpu);
+
 	return clk_bulk_prepare_enable(QSPI_NUM_CLKS, ctrl->clks);
 }
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

Re: [PATCH 5/6] spi: spi-qcom-qspi: Add interconnect support

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 548 bytes --]

On Mon, Feb 17, 2020 at 07:00:04PM +0530, Akash Asthana wrote:
> Get the interconnect paths for QSPI device and vote according to the
> current bus speed of the driver.

Acked-by: Mark Brown <broonie@kernel.org>

> +	/* Set BW quota for CPU as driver supports FIFO mode only */
> +	ctrl->avg_bw_cpu = Bps_to_icc(speed_hz);
> +	ctrl->peak_bw_cpu = Bps_to_icc(2 * speed_hz);

These peak numbers seem like you're just guessing and should perhaps be
handled more gracefully by the core (eg, assuming twice the average if
no explicit peak is provided).

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[PATCH 6/6] arm64: dts: sc7180: Add interconnect for QUP and QSPI

[Akash Asthana]

Add interconnect ports for GENI QUPs and QSPI to set bus capabilities.

Signed-off-by: Akash Asthana <akashast@codeaurora.org>
---
Note:
 - This patch depends on series https://patchwork.kernel.org/cover/11313817/
   [Add SC7180 interconnect provider driver]. It won't compile without that.

 arch/arm64/boot/dts/qcom/sc7180.dtsi | 199 +++++++++++++++++++++++++++++++++++
 1 file changed, 199 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index cc5a94f..04569c9 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -352,6 +352,14 @@
 				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>,
+						<&aggre1_noc MASTER_QUP_0
+						&mc_virt SLAVE_EBI1>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
 				status = "disabled";
 			};
 
@@ -365,6 +373,11 @@
 				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -376,6 +389,11 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart0_default>;
 				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -389,6 +407,14 @@
 				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>,
+						<&aggre1_noc MASTER_QUP_0
+						&mc_virt SLAVE_EBI1>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
 				status = "disabled";
 			};
 
@@ -402,6 +428,11 @@
 				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -413,6 +444,11 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart1_default>;
 				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -426,6 +462,14 @@
 				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>,
+						<&aggre1_noc MASTER_QUP_0
+						&mc_virt SLAVE_EBI1>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
 				status = "disabled";
 			};
 
@@ -437,6 +481,11 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart2_default>;
 				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -450,6 +499,14 @@
 				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>,
+						<&aggre1_noc MASTER_QUP_0
+						&mc_virt SLAVE_EBI1>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
 				status = "disabled";
 			};
 
@@ -463,6 +520,11 @@
 				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -474,6 +536,11 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart3_default>;
 				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -487,6 +554,14 @@
 				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>,
+						<&aggre1_noc MASTER_QUP_0
+						&mc_virt SLAVE_EBI1>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
 				status = "disabled";
 			};
 
@@ -498,6 +573,11 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart4_default>;
 				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -511,6 +591,14 @@
 				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>,
+						<&aggre1_noc MASTER_QUP_0
+						&mc_virt SLAVE_EBI1>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
 				status = "disabled";
 			};
 
@@ -524,6 +612,11 @@
 				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -535,6 +628,11 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart5_default>;
 				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_0
+						&qup_virt SLAVE_QUP_CORE_0>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_0>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 		};
@@ -561,6 +659,14 @@
 				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>,
+						<&aggre2_noc MASTER_QUP_1
+						&mc_virt SLAVE_EBI1>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
 				status = "disabled";
 			};
 
@@ -574,6 +680,11 @@
 				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -585,6 +696,11 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart6_default>;
 				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -598,6 +714,14 @@
 				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>,
+						<&aggre2_noc MASTER_QUP_1
+						&mc_virt SLAVE_EBI1>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
 				status = "disabled";
 			};
 
@@ -609,6 +733,11 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart7_default>;
 				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -622,6 +751,14 @@
 				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>,
+						<&aggre2_noc MASTER_QUP_1
+						&mc_virt SLAVE_EBI1>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
 				status = "disabled";
 			};
 
@@ -635,6 +772,11 @@
 				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -646,6 +788,11 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart8_default>;
 				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -659,6 +806,14 @@
 				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>,
+						<&aggre2_noc MASTER_QUP_1
+						&mc_virt SLAVE_EBI1>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
 				status = "disabled";
 			};
 
@@ -670,6 +825,11 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart9_default>;
 				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -683,6 +843,14 @@
 				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>,
+						<&aggre2_noc MASTER_QUP_1
+						&mc_virt SLAVE_EBI1>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
 				status = "disabled";
 			};
 
@@ -696,6 +864,11 @@
 				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -707,6 +880,11 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart10_default>;
 				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -720,6 +898,14 @@
 				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>,
+						<&aggre2_noc MASTER_QUP_1
+						&mc_virt SLAVE_EBI1>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
 				status = "disabled";
 			};
 
@@ -733,6 +919,11 @@
 				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -744,6 +935,11 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&qup_uart11_default>;
 				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&qup_virt MASTER_QUP_CORE_1
+						&qup_virt SLAVE_QUP_CORE_1>,
+						<&gem_noc MASTER_APPSS_PROC
+						&config_noc SLAVE_QUP_1>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 		};
@@ -1051,6 +1247,9 @@
 			clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
 				 <&gcc GCC_QSPI_CORE_CLK>;
 			clock-names = "iface", "core";
+			interconnects = <&gem_noc MASTER_APPSS_PROC
+					&config_noc SLAVE_QSPI_0>;
+			interconnect-names = "qspi-config";
 			status = "disabled";
 		};
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

Re: [PATCH 6/6] arm64: dts: sc7180: Add interconnect for QUP and QSPI

[Bjorn Andersson]

On Mon 17 Feb 05:30 PST 2020, Akash Asthana wrote:

> Add interconnect ports for GENI QUPs and QSPI to set bus capabilities.
> 
> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> ---
> Note:
>  - This patch depends on series https://patchwork.kernel.org/cover/11313817/
>    [Add SC7180 interconnect provider driver]. It won't compile without that.
> 
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 199 +++++++++++++++++++++++++++++++++++
>  1 file changed, 199 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index cc5a94f..04569c9 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -352,6 +352,14 @@
>  				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
>  				#address-cells = <1>;
>  				#size-cells = <0>;
> +				interconnects = <&qup_virt MASTER_QUP_CORE_0
> +						&qup_virt SLAVE_QUP_CORE_0>,
> +						<&gem_noc MASTER_APPSS_PROC
> +						&config_noc SLAVE_QUP_0>,
> +						<&aggre1_noc MASTER_QUP_0
> +						&mc_virt SLAVE_EBI1>;

Please ignore the 80-char "limit" and write this as:
				interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
						<&gem_noc ...>,
						<&aggre1_noc ...>;

Regards,
Bjorn

Re: [PATCH 6/6] arm64: dts: sc7180: Add interconnect for QUP and QSPI

[Akash Asthana]

Hi Bjorn,

>> +				interconnects = <&qup_virt MASTER_QUP_CORE_0
>> +						&qup_virt SLAVE_QUP_CORE_0>,
>> +						<&gem_noc MASTER_APPSS_PROC
>> +						&config_noc SLAVE_QUP_0>,
>> +						<&aggre1_noc MASTER_QUP_0
>> +						&mc_virt SLAVE_EBI1>;
> Please ignore the 80-char "limit" and write this as:
> 				interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
> 						<&gem_noc ...>,
> 						<&aggre1_noc ...>;
>
> Regards,
> Bjorn

ok

Regards,

Akash

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

Re: [PATCH 6/6] arm64: dts: sc7180: Add interconnect for QUP and QSPI

[Amit Kucheria]

Hi Akash,


On Mon, Feb 17, 2020 at 7:01 PM Akash Asthana <akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:
>
> Add interconnect ports for GENI QUPs and QSPI to set bus capabilities.
>
> Signed-off-by: Akash Asthana <akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
> Note:
>  - This patch depends on series https://patchwork.kernel.org/cover/11313817/
>    [Add SC7180 interconnect provider driver]. It won't compile without that.

I've tried picking up v4 of Odelu's series to add the SC7180 but I'm
still unable to compile this. I see the following error:

Error: /home/amit/work/sources/worktree-review-pipeline/arch/arm64/boot/dts/qcom/sc7180.dtsi:353.32-33
syntax error
FATAL ERROR: Unable to parse input tree
make[3]: *** [scripts/Makefile.lib:296:
arch/arm64/boot/dts/qcom/sc7180-idp.dtb] Error 1

As part of picking up the dependencies, I've pulled the following
series on top of v5.6-rc2:

- https://lore.kernel.org/r/1581932974-21654-2-git-send-email-akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org
- https://lore.kernel.org/r/1581932212-19469-2-git-send-email-akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org
- https://lore.kernel.org/r/1581946205-27189-2-git-send-email-akashast-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org
- https://lore.kernel.org/r/1582646384-1458-2-git-send-email-okukatla-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org
- https://lore.kernel.org/r/20200209183411.17195-2-sibis-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org

What am I missing?

I've pushed the aggregate branch here for convenience:
https://git.linaro.org/people/amit.kucheria/kernel.git/log/

Regards,
Amit

>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 199 +++++++++++++++++++++++++++++++++++
>  1 file changed, 199 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index cc5a94f..04569c9 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -352,6 +352,14 @@
>                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>,
> +                                               <&aggre1_noc MASTER_QUP_0
> +                                               &mc_virt SLAVE_EBI1>;
> +                               interconnect-names = "qup-core", "qup-config",
> +                                                       "qup-memory";
>                                 status = "disabled";
>                         };
>
> @@ -365,6 +373,11 @@
>                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -376,6 +389,11 @@
>                                 pinctrl-names = "default";
>                                 pinctrl-0 = <&qup_uart0_default>;
>                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -389,6 +407,14 @@
>                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>,
> +                                               <&aggre1_noc MASTER_QUP_0
> +                                               &mc_virt SLAVE_EBI1>;
> +                               interconnect-names = "qup-core", "qup-config",
> +                                                       "qup-memory";
>                                 status = "disabled";
>                         };
>
> @@ -402,6 +428,11 @@
>                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -413,6 +444,11 @@
>                                 pinctrl-names = "default";
>                                 pinctrl-0 = <&qup_uart1_default>;
>                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -426,6 +462,14 @@
>                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>,
> +                                               <&aggre1_noc MASTER_QUP_0
> +                                               &mc_virt SLAVE_EBI1>;
> +                               interconnect-names = "qup-core", "qup-config",
> +                                                       "qup-memory";
>                                 status = "disabled";
>                         };
>
> @@ -437,6 +481,11 @@
>                                 pinctrl-names = "default";
>                                 pinctrl-0 = <&qup_uart2_default>;
>                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -450,6 +499,14 @@
>                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>,
> +                                               <&aggre1_noc MASTER_QUP_0
> +                                               &mc_virt SLAVE_EBI1>;
> +                               interconnect-names = "qup-core", "qup-config",
> +                                                       "qup-memory";
>                                 status = "disabled";
>                         };
>
> @@ -463,6 +520,11 @@
>                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -474,6 +536,11 @@
>                                 pinctrl-names = "default";
>                                 pinctrl-0 = <&qup_uart3_default>;
>                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -487,6 +554,14 @@
>                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>,
> +                                               <&aggre1_noc MASTER_QUP_0
> +                                               &mc_virt SLAVE_EBI1>;
> +                               interconnect-names = "qup-core", "qup-config",
> +                                                       "qup-memory";
>                                 status = "disabled";
>                         };
>
> @@ -498,6 +573,11 @@
>                                 pinctrl-names = "default";
>                                 pinctrl-0 = <&qup_uart4_default>;
>                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -511,6 +591,14 @@
>                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>,
> +                                               <&aggre1_noc MASTER_QUP_0
> +                                               &mc_virt SLAVE_EBI1>;
> +                               interconnect-names = "qup-core", "qup-config",
> +                                                       "qup-memory";
>                                 status = "disabled";
>                         };
>
> @@ -524,6 +612,11 @@
>                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -535,6 +628,11 @@
>                                 pinctrl-names = "default";
>                                 pinctrl-0 = <&qup_uart5_default>;
>                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> +                                               &qup_virt SLAVE_QUP_CORE_0>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_0>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>                 };
> @@ -561,6 +659,14 @@
>                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>,
> +                                               <&aggre2_noc MASTER_QUP_1
> +                                               &mc_virt SLAVE_EBI1>;
> +                               interconnect-names = "qup-core", "qup-config",
> +                                                       "qup-memory";
>                                 status = "disabled";
>                         };
>
> @@ -574,6 +680,11 @@
>                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -585,6 +696,11 @@
>                                 pinctrl-names = "default";
>                                 pinctrl-0 = <&qup_uart6_default>;
>                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -598,6 +714,14 @@
>                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>,
> +                                               <&aggre2_noc MASTER_QUP_1
> +                                               &mc_virt SLAVE_EBI1>;
> +                               interconnect-names = "qup-core", "qup-config",
> +                                                       "qup-memory";
>                                 status = "disabled";
>                         };
>
> @@ -609,6 +733,11 @@
>                                 pinctrl-names = "default";
>                                 pinctrl-0 = <&qup_uart7_default>;
>                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -622,6 +751,14 @@
>                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>,
> +                                               <&aggre2_noc MASTER_QUP_1
> +                                               &mc_virt SLAVE_EBI1>;
> +                               interconnect-names = "qup-core", "qup-config",
> +                                                       "qup-memory";
>                                 status = "disabled";
>                         };
>
> @@ -635,6 +772,11 @@
>                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -646,6 +788,11 @@
>                                 pinctrl-names = "default";
>                                 pinctrl-0 = <&qup_uart8_default>;
>                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -659,6 +806,14 @@
>                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>,
> +                                               <&aggre2_noc MASTER_QUP_1
> +                                               &mc_virt SLAVE_EBI1>;
> +                               interconnect-names = "qup-core", "qup-config",
> +                                                       "qup-memory";
>                                 status = "disabled";
>                         };
>
> @@ -670,6 +825,11 @@
>                                 pinctrl-names = "default";
>                                 pinctrl-0 = <&qup_uart9_default>;
>                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -683,6 +843,14 @@
>                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>,
> +                                               <&aggre2_noc MASTER_QUP_1
> +                                               &mc_virt SLAVE_EBI1>;
> +                               interconnect-names = "qup-core", "qup-config",
> +                                                       "qup-memory";
>                                 status = "disabled";
>                         };
>
> @@ -696,6 +864,11 @@
>                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -707,6 +880,11 @@
>                                 pinctrl-names = "default";
>                                 pinctrl-0 = <&qup_uart10_default>;
>                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -720,6 +898,14 @@
>                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>,
> +                                               <&aggre2_noc MASTER_QUP_1
> +                                               &mc_virt SLAVE_EBI1>;
> +                               interconnect-names = "qup-core", "qup-config",
> +                                                       "qup-memory";
>                                 status = "disabled";
>                         };
>
> @@ -733,6 +919,11 @@
>                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>
> @@ -744,6 +935,11 @@
>                                 pinctrl-names = "default";
>                                 pinctrl-0 = <&qup_uart11_default>;
>                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> +                                               &qup_virt SLAVE_QUP_CORE_1>,
> +                                               <&gem_noc MASTER_APPSS_PROC
> +                                               &config_noc SLAVE_QUP_1>;
> +                               interconnect-names = "qup-core", "qup-config";
>                                 status = "disabled";
>                         };
>                 };
> @@ -1051,6 +1247,9 @@
>                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
>                                  <&gcc GCC_QSPI_CORE_CLK>;
>                         clock-names = "iface", "core";
> +                       interconnects = <&gem_noc MASTER_APPSS_PROC
> +                                       &config_noc SLAVE_QSPI_0>;
> +                       interconnect-names = "qspi-config";
>                         status = "disabled";
>                 };
>
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project

Re: [PATCH 6/6] arm64: dts: sc7180: Add interconnect for QUP and QSPI

[Matthias Kaehlcke]

Hi Amit,

the following include is missing:

#include <dt-bindings/interconnect/qcom,sc7180.h>

It was added in v2 of "arm64: dts: sc7180: Add interconnect provider DT.
nodes", but removed in later versions. v2 had a comment requesting to move
the include one line up, my guess is it got lost while doing that.

On Thu, Feb 27, 2020 at 05:41:03PM +0530, Amit Kucheria wrote:
> Hi Akash,
> 
> 
> On Mon, Feb 17, 2020 at 7:01 PM Akash Asthana <akashast@codeaurora.org> wrote:
> >
> > Add interconnect ports for GENI QUPs and QSPI to set bus capabilities.
> >
> > Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> > ---
> > Note:
> >  - This patch depends on series https://patchwork.kernel.org/cover/11313817/
> >    [Add SC7180 interconnect provider driver]. It won't compile without that.
> 
> I've tried picking up v4 of Odelu's series to add the SC7180 but I'm
> still unable to compile this. I see the following error:
> 
> Error: /home/amit/work/sources/worktree-review-pipeline/arch/arm64/boot/dts/qcom/sc7180.dtsi:353.32-33
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[3]: *** [scripts/Makefile.lib:296:
> arch/arm64/boot/dts/qcom/sc7180-idp.dtb] Error 1
> 
> As part of picking up the dependencies, I've pulled the following
> series on top of v5.6-rc2:
> 
> - https://lore.kernel.org/r/1581932974-21654-2-git-send-email-akashast@codeaurora.org
> - https://lore.kernel.org/r/1581932212-19469-2-git-send-email-akashast@codeaurora.org
> - https://lore.kernel.org/r/1581946205-27189-2-git-send-email-akashast@codeaurora.org
> - https://lore.kernel.org/r/1582646384-1458-2-git-send-email-okukatla@codeaurora.org
> - https://lore.kernel.org/r/20200209183411.17195-2-sibis@codeaurora.org
> 
> What am I missing?
> 
> I've pushed the aggregate branch here for convenience:
> https://git.linaro.org/people/amit.kucheria/kernel.git/log/
> 
> Regards,
> Amit
> 
> >  arch/arm64/boot/dts/qcom/sc7180.dtsi | 199 +++++++++++++++++++++++++++++++++++
> >  1 file changed, 199 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > index cc5a94f..04569c9 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > @@ -352,6 +352,14 @@
> >                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>,
> > +                                               <&aggre1_noc MASTER_QUP_0
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -365,6 +373,11 @@
> >                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -376,6 +389,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart0_default>;
> >                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -389,6 +407,14 @@
> >                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>,
> > +                                               <&aggre1_noc MASTER_QUP_0
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -402,6 +428,11 @@
> >                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -413,6 +444,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart1_default>;
> >                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -426,6 +462,14 @@
> >                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>,
> > +                                               <&aggre1_noc MASTER_QUP_0
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -437,6 +481,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart2_default>;
> >                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -450,6 +499,14 @@
> >                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>,
> > +                                               <&aggre1_noc MASTER_QUP_0
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -463,6 +520,11 @@
> >                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -474,6 +536,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart3_default>;
> >                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -487,6 +554,14 @@
> >                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>,
> > +                                               <&aggre1_noc MASTER_QUP_0
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -498,6 +573,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart4_default>;
> >                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -511,6 +591,14 @@
> >                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>,
> > +                                               <&aggre1_noc MASTER_QUP_0
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -524,6 +612,11 @@
> >                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -535,6 +628,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart5_default>;
> >                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >                 };
> > @@ -561,6 +659,14 @@
> >                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>,
> > +                                               <&aggre2_noc MASTER_QUP_1
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -574,6 +680,11 @@
> >                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -585,6 +696,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart6_default>;
> >                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -598,6 +714,14 @@
> >                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>,
> > +                                               <&aggre2_noc MASTER_QUP_1
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -609,6 +733,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart7_default>;
> >                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -622,6 +751,14 @@
> >                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>,
> > +                                               <&aggre2_noc MASTER_QUP_1
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -635,6 +772,11 @@
> >                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -646,6 +788,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart8_default>;
> >                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -659,6 +806,14 @@
> >                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>,
> > +                                               <&aggre2_noc MASTER_QUP_1
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -670,6 +825,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart9_default>;
> >                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -683,6 +843,14 @@
> >                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>,
> > +                                               <&aggre2_noc MASTER_QUP_1
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -696,6 +864,11 @@
> >                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -707,6 +880,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart10_default>;
> >                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -720,6 +898,14 @@
> >                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>,
> > +                                               <&aggre2_noc MASTER_QUP_1
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -733,6 +919,11 @@
> >                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -744,6 +935,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart11_default>;
> >                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >                 };
> > @@ -1051,6 +1247,9 @@
> >                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
> >                                  <&gcc GCC_QSPI_CORE_CLK>;
> >                         clock-names = "iface", "core";
> > +                       interconnects = <&gem_noc MASTER_APPSS_PROC
> > +                                       &config_noc SLAVE_QSPI_0>;
> > +                       interconnect-names = "qspi-config";
> >                         status = "disabled";
> >                 };
> >
> > --
> > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project