IT8716F SPI driver submission?

IT8716F SPI driver submission?

[Carl-Daniel Hailfinger]

Hi!

I have written a rough code skeleton to be able to use the ITE IT8716F
Super I/O chip as SPI host/master. The code works fine in userspace, but
the Linux kernel SPI framework looks like it could save me from
implementing full support for SPI flash clients/slaves. That's why I'd
like to rewrite my code in a manner that's suitable for kernel inclusion.

The IT8716F accepts commands byte-wise and does all of the lifting on
the SPI bus as well. There are limitations, though:
- It can send 1,2,4,5 bytes (including command byte) to the slave and
read 0,1,2,3 bytes back. Other values are not possible.
- Bus clock rate is either 33 MHz or 16.5 MHz.

Is there any driver I can start from as reference?

Regards,
Carl-Daniel

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Re: IT8716F SPI driver submission?

[David Brownell]

> The IT8716F accepts commands byte-wise and does all of the lifting on
> the SPI bus as well. There are limitations, though:
> - It can send 1,2,4,5 bytes (including command byte) to the slave and
> read 0,1,2,3 bytes back. Other values are not possible.
> - Bus clock rate is either 33 MHz or 16.5 MHz.
>
> Is there any driver I can start from as reference?

None that I know of.  You might find it's easier to just work with
a bastardized version of the (latest, with the 2.6.24 MTD updates
so it handleds even more chips) m25p80 driver and not go through the
SPI framework.  It doesn't look like you could even bitbang SPI there,
since not all those pins are usable for bit-level I/O.

As you note, that hardware doesn't support all that a SPI controller
does.  It's provided for accessing a single serial flash chip; and
not even to do that very smoothly.  You'd have to somehow prevent that
driver from reading or writing normal size blocks.  And you'd need to
defend against drivers trying to do full duplex or multi-segment I/O
requests, etc.  Lots more work than a bastardized m25p80 driver.  ;)

My limited exposure to SPI on PC hardware -- LPC chips like this, and
newer southbridges -- suggests they tend to be just as, erm, "limited"
as this one in terms of supporting anything other than one particular
variety of serial flash interface.  I think the idea was just to let
board makers use cheaper flash chips when loading the BIOS.  For that,
they don't need the kind of flexible expansion bus SPI is on most SOC
chips; or much throughput.

- Dave


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