[patch 2.6.24-rc2 2/3] atmel_spi throughput improvement

[patch 2.6.24-rc2 2/3] atmel_spi throughput improvement

[David Brownell]

From: Haavard Skinnemoen <hskinnemoen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>

Don't insert (undesirable) delays between consecutive words (DLYBCT)
or when activating chipselects (DLYBS).

Removing the between-word delays improves the performance of bulk
transfers (such as mtd_dataflash, m25p80, mmc_spi) significantly.
In one test, the improvement was a factor of more than eight!

(The large DLYBCT value came from the legacy at91 SPI driver, and
it's not clear why it used such a huge value.)

Signed-off-by: Haavard Skinnemoen <hskinnemoen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
---
 drivers/spi/atmel_spi.c |   11 ++++++++---
 1 files changed, 8 insertions(+), 3 deletions(-)

--- a/drivers/spi/atmel_spi.c	2007-11-14 14:59:43.000000000 -0800
+++ b/drivers/spi/atmel_spi.c	2007-11-14 15:03:30.000000000 -0800
@@ -490,9 +490,14 @@ static int atmel_spi_setup(struct spi_de
 	if (!(spi->mode & SPI_CPHA))
 		csr |= SPI_BIT(NCPHA);
 
-	/* TODO: DLYBS and DLYBCT */
-	csr |= SPI_BF(DLYBS, 10);
-	csr |= SPI_BF(DLYBCT, 10);
+	/* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
+	 *
+	 * DLYBCT would add delays between words, slowing down transfers.
+	 * It could potentially be useful to cope with DMA bottlenecks, but
+	 * in those cases it's probably best to just use a lower bitrate.
+	 */
+	csr |= SPI_BF(DLYBS, 0);
+	csr |= SPI_BF(DLYBCT, 0);
 
 	/* chipselect must have been muxed as GPIO (e.g. in board setup) */
 	npcs_pin = (unsigned int)spi->controller_data;

-------------------------------------------------------------------------
This SF.net email is sponsored by: Splunk Inc.
Still grepping through log files to find problems?  Stop.
Now Search log events and configuration files using AJAX and a browser.
Download your FREE copy of Splunk now >> http://get.splunk.com/