From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH 7/9] ARM: dts: sun5i: add SPI pins on A13 and A10s Date: Thu, 20 Aug 2015 17:00:57 +0200 Message-ID: <20150820150057.GY30520@lukather> References: <90730047894f6ec84cd70062a27b7085c2016260.1440080122.git.hramrach@gmail.com> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="vavxEBoGuREFpPEl" Cc: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Mark Brown , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Michal Suchanek Return-path: Content-Disposition: inline In-Reply-To: <90730047894f6ec84cd70062a27b7085c2016260.1440080122.git.hramrach-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , List-Id: linux-spi.vger.kernel.org --vavxEBoGuREFpPEl Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline On Thu, Aug 20, 2015 at 02:19:47PM -0000, Michal Suchanek wrote: > According to datasheet some pins are available on A10s only while others > are shared with A13. > > Signed-off-by: Michal Suchanek > --- > This time add all spi pins and make the CS pins separate as is seen with > current sun4i DTs > --- > arch/arm/boot/dts/sun5i-a10s.dtsi | 21 +++++++++++++++++ > arch/arm/boot/dts/sun5i.dtsi | 49 +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 70 insertions(+) > > diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi > index f11efb7..d9610fa 100644 > --- a/arch/arm/boot/dts/sun5i-a10s.dtsi > +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi > @@ -201,6 +201,27 @@ > allwinner,drive = ; > allwinner,pull = ; > }; > + > + spi1_cs1_pins_a: spi1_cs1@0 { > + allwinner,pins = "PG13"; > + allwinner,function = "spi1"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + spi2_pins_a: spi2@0 { > + allwinner,pins = "PB12", "PB13", "PB14"; > + allwinner,function = "spi1"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + spi2_cs0_pins_a: spi2_cs0@0 { > + allwinner,pins = "PB11"; > + allwinner,function = "spi1"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; spi2 nodes with spi1 function ??? How can that even work? > }; > > &sram_a { > diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi > index 54b0978..7d32d49 100644 > --- a/arch/arm/boot/dts/sun5i.dtsi > +++ b/arch/arm/boot/dts/sun5i.dtsi > @@ -516,6 +516,55 @@ > allwinner,drive = ; > allwinner,pull = ; > }; > + > + spi0_pins_a: spi0@0 { > + allwinner,pins = "PC00", "PC01", "PC02"; > + allwinner,function = "spi0"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + spi0_cs0_pins_a: spi0_cs0@0 { > + allwinner,pins = "PC03"; > + allwinner,function = "spi0"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + spi1_pins_a: spi1@0 { > + allwinner,pins = "PG10", "PG11", "PG12"; > + allwinner,function = "spi1"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + spi1_cs0_pins_a: spi1_cs0@0 { > + allwinner,pins = "PG09"; > + allwinner,function = "spi1"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + spi2_pins_b: spi2@1 { > + allwinner,pins = "PE01", "PE02", "PE03"; > + allwinner,function = "spi2"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + spi2_cs0_pins_b: spi2_cs1@1 { > + allwinner,pins = "PE00"; > + allwinner,function = "spi2"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + spi2_cs1_pins_a: spi2_cs1@0 { > + allwinner,pins = "PB10"; > + allwinner,function = "spi2"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; Please only add the pins you intend to use. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --vavxEBoGuREFpPEl--