From: H Hartley Sweeten <hsweeten-3FF4nKcrg1dE2c76skzGb0EOCMrvLtNR@public.gmane.org>
To: linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: H Hartley Sweeten
<hsweeten-3FF4nKcrg1dE2c76skzGb0EOCMrvLtNR@public.gmane.org>
Subject: [PATCH 4/7] spi: spi-ep93xx: absorb the interrupt enable/disable helpers
Date: Thu, 16 Feb 2017 16:48:48 -0700 [thread overview]
Message-ID: <20170216234851.97938-5-hsweeten@visionengravers.com> (raw)
In-Reply-To: <20170216234851.97938-1-hsweeten-3FF4nKcrg1dE2c76skzGb0EOCMrvLtNR@public.gmane.org>
These are each only called once. Just absorb them into the callers.
Signed-off-by: H Hartley Sweeten <hsweeten-3FF4nKcrg1dE2c76skzGb0EOCMrvLtNR@public.gmane.org>
---
drivers/spi/spi-ep93xx.c | 32 ++++++++++++--------------------
1 file changed, 12 insertions(+), 20 deletions(-)
diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c
index dd179f3..e8f454b 100644
--- a/drivers/spi/spi-ep93xx.c
+++ b/drivers/spi/spi-ep93xx.c
@@ -111,24 +111,6 @@ struct ep93xx_spi {
/* converts bits per word to CR0.DSS value */
#define bits_per_word_to_dss(bpw) ((bpw) - 1)
-static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi)
-{
- unsigned int val;
-
- val = readl(espi->mmio + SSPCR1);
- val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
- writel(val, espi->mmio + SSPCR1);
-}
-
-static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
-{
- unsigned int val;
-
- val = readl(espi->mmio + SSPCR1);
- val &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
- writel(val, espi->mmio + SSPCR1);
-}
-
/**
* ep93xx_spi_calc_divisors() - calculates SPI clock divisors
* @espi: ep93xx SPI controller struct
@@ -282,7 +264,12 @@ static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi)
* FIFO, enable interrupts, and wait for the transfer to complete.
*/
if (ep93xx_spi_read_write(espi)) {
- ep93xx_spi_enable_interrupts(espi);
+ unsigned int val;
+
+ val = readl(espi->mmio + SSPCR1);
+ val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
+ writel(val, espi->mmio + SSPCR1);
+
wait_for_completion(&espi->wait);
}
}
@@ -604,6 +591,7 @@ static int ep93xx_spi_transfer_one_message(struct spi_master *master,
static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
{
struct ep93xx_spi *espi = dev_id;
+ unsigned int val;
/*
* If we got ROR (receive overrun) interrupt we know that something is
@@ -635,8 +623,12 @@ static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
* any case we disable interrupts and notify the worker to handle
* any post-processing of the message.
*/
- ep93xx_spi_disable_interrupts(espi);
+ val = readl(espi->mmio + SSPCR1);
+ val &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
+ writel(val, espi->mmio + SSPCR1);
+
complete(&espi->wait);
+
return IRQ_HANDLED;
}
--
2.10.0
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next prev parent reply other threads:[~2017-02-16 23:48 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-16 23:48 [PATCH 0/7] spi: spi-ep93xx: cleanup and update driver to modern API H Hartley Sweeten
[not found] ` <20170216234851.97938-1-hsweeten-3FF4nKcrg1dE2c76skzGb0EOCMrvLtNR@public.gmane.org>
2017-02-16 23:48 ` [PATCH 1/7] spi: spi-ep93xx: remove io wrappers H Hartley Sweeten
[not found] ` <20170216234851.97938-2-hsweeten-3FF4nKcrg1dE2c76skzGb0EOCMrvLtNR@public.gmane.org>
2017-08-09 16:57 ` Applied "spi: spi-ep93xx: remove io wrappers" to the spi tree Mark Brown
2017-02-16 23:48 ` [PATCH 2/7] spi: spi-ep93xx: use 32-bit read/write for all registers H Hartley Sweeten
2017-02-16 23:48 ` [PATCH 3/7] spi: spi-ep93xx: add spi master prepare_transfer_hardware() H Hartley Sweeten
2017-02-16 23:48 ` H Hartley Sweeten [this message]
2017-02-16 23:48 ` [PATCH 5/7] spi: spi-ep93xx: pass the spi_master pointer around H Hartley Sweeten
2017-02-16 23:48 ` [PATCH 6/7] spi: spi-ep93xx: remove private data 'current_msg' H Hartley Sweeten
[not found] ` <20170216234851.97938-7-hsweeten-3FF4nKcrg1dE2c76skzGb0EOCMrvLtNR@public.gmane.org>
2017-08-09 16:57 ` Applied "spi: spi-ep93xx: remove private data 'current_msg'" to the spi tree Mark Brown
2017-02-16 23:48 ` [PATCH 7/7] spi: spi-ep93xx: use the default master transfer queueing mechanism H Hartley Sweeten
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