From: Hieu Tran Dang <dangtranhieu2012@gmail.com>
To: Mark Brown <broonie@kernel.org>
Cc: Hieu Tran Dang <dangtranhieu2012@gmail.com>,
linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH] spi: fsl-lpspi: Prevent FIFO under/overrun by default
Date: Tue, 2 Oct 2018 18:06:36 +0700 [thread overview]
Message-ID: <20181002110636.5052-1-dangtranhieu2012@gmail.com> (raw)
Certain devices don't work well when a transmit FIFO underrun or
receive FIFO overrun occurs. Example is the SAF400x radio chip when
running at high speed which leads to garbage being sent to/received from
the chip. In which case, it should stall waiting for further data to be
available before proceeding. This patch unset the NOSTALL bit in CFGR1
by default to prevent this issue.
Signed-off-by: Hieu Tran Dang <dangtranhieu2012@gmail.com>
---
drivers/spi/spi-fsl-lpspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index e6d5cc6ab108..51670976faa3 100644
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -276,7 +276,7 @@ static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
fsl_lpspi_set_watermark(fsl_lpspi);
- temp = CFGR1_PCSCFG | CFGR1_MASTER | CFGR1_NOSTALL;
+ temp = CFGR1_PCSCFG | CFGR1_MASTER;
if (fsl_lpspi->config.mode & SPI_CS_HIGH)
temp |= CFGR1_PCSPOL;
writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
--
2.17.1
next reply other threads:[~2018-10-02 11:06 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-02 11:06 Hieu Tran Dang [this message]
2018-10-10 14:52 ` Applied "spi: fsl-lpspi: Prevent FIFO under/overrun by default" to the spi tree Mark Brown
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