From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lubomir Rintel Subject: [PATCH v2 01/11] dt-bindings: spi/spi-pxa2xx: add PXA2xx SSP SPI Controller Date: Wed, 10 Oct 2018 19:09:26 +0200 Message-ID: <20181010170936.316862-2-lkundrak@v3.sk> References: <20181010170936.316862-1-lkundrak@v3.sk> Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Cc: James Cameron , Rob Herring , Mark Rutland , Eric Miao , Haojian Zhuang , Daniel Mack , Robert Jarzmik , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Lubomir Rintel To: Mark Brown , Geert Uytterhoeven Return-path: In-Reply-To: <20181010170936.316862-1-lkundrak@v3.sk> Sender: linux-kernel-owner@vger.kernel.org List-Id: linux-spi.vger.kernel.org This is the SPI controller found on Marvel MMP2 and perhaps more platforms. Reviewed-by: Rob Herring Signed-off-by: Lubomir Rintel --- Changes since v1: - s/ssp@d4035000/spi@d4035000/ .../devicetree/bindings/spi/spi-pxa2xx.txt | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-pxa2xx.txt diff --git a/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt b/Docum= entation/devicetree/bindings/spi/spi-pxa2xx.txt new file mode 100644 index 000000000000..0335a9bd2e8a --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt @@ -0,0 +1,24 @@ +PXA2xx SSP SPI Controller + +Required properties: +- compatible: Must be "marvell,mmp2-ssp". +- reg: Offset and length of the device's register set. +- interrupts: Should be the interrupt number. +- clocks: Should contain a single entry describing the clock input. +- #address-cells: Number of cells required to define a chip select addr= ess. +- #size-cells: Should be zero. + +Optional properties: +- cs-gpios: list of GPIO chip selects. See the SPI bus bindings, + Documentation/devicetree/bindings/spi/spi-bus.txt + +Child nodes represent devices on the SPI bus + See ../spi/spi-bus.txt + +Example: + ssp1: spi@d4035000 { + compatible =3D "marvell,mmp2-ssp"; + reg =3D <0xd4035000 0x1000>; + clocks =3D <&soc_clocks MMP2_CLK_SSP0>; + interrupts =3D <0>; + }; --=20 2.19.0