From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Mark Brown <broonie@kernel.org>,
linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Ludovic Desroches <ludovic.desroches@microchip.com>,
linux-arm-kernel@lists.infradead.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Gregory CLEMENT <gregory.clement@bootlin.com>
Subject: [PATCH 1/7] spi: atmel: Remove and fix erroneous comments
Date: Thu, 17 Oct 2019 16:18:40 +0200 [thread overview]
Message-ID: <20191017141846.7523-2-gregory.clement@bootlin.com> (raw)
In-Reply-To: <20191017141846.7523-1-gregory.clement@bootlin.com>
Since CSAAT functionality support has been added. Some comments become
wrong. Fix them to match the current driver behavior.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
drivers/spi/spi-atmel.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index e34ab587b980..7a17c3e2a8ee 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -312,11 +312,9 @@ static bool atmel_spi_is_v2(struct atmel_spi *as)
* transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
* controllers have CSAAT and friends.
*
- * Since the CSAAT functionality is a bit weird on newer controllers as
- * well, we use GPIO to control nCSx pins on all controllers, updating
- * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
- * support active-high chipselects despite the controller's belief that
- * only active-low devices/systems exists.
+ * Even controller newer than ar91rm9200, using GPIOs can make sens as
+ * it lets us support active-high chipselects despite the controller's
+ * belief that only active-low devices/systems exists.
*
* However, at91rm9200 has a second erratum whereby nCS0 doesn't work
* right when driven with GPIO. ("Mode Fault does not allow more than one
@@ -1193,8 +1191,6 @@ static int atmel_spi_setup(struct spi_device *spi)
if (!as->use_cs_gpios)
csr |= SPI_BIT(CSAAT);
- /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
- */
csr |= SPI_BF(DLYBS, 0);
word_delay_csr = atmel_word_delay_csr(spi, as);
--
2.23.0
next prev parent reply other threads:[~2019-10-17 14:18 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-17 14:18 [PATCH 0/7] atmel-spi: Allow using more than 4 GPIOs as CS Gregory CLEMENT
2019-10-17 14:18 ` Gregory CLEMENT [this message]
2019-10-18 18:07 ` Applied "spi: atmel: Remove and fix erroneous comments" to the spi tree Mark Brown
2019-10-17 14:18 ` [PATCH 2/7] spi: atmel: Fix CS high support Gregory CLEMENT
2019-10-18 18:07 ` Applied "spi: atmel: Fix CS high support" to the spi tree Mark Brown
2019-10-17 14:18 ` [PATCH 3/7] spi: atmel: Configure GPIO per CS instead of by controller Gregory CLEMENT
2019-10-18 18:07 ` Applied "spi: atmel: Configure GPIO per CS instead of by controller" to the spi tree Mark Brown
2019-10-17 14:18 ` [PATCH 4/7] spi: atmel: Remove useless private field Gregory CLEMENT
2019-10-18 18:07 ` Applied "spi: atmel: Remove useless private field" to the spi tree Mark Brown
2019-10-17 14:18 ` [PATCH 5/7] spi: atmel: Remove platform data support Gregory CLEMENT
2019-10-18 18:07 ` Applied "spi: atmel: Remove platform data support" to the spi tree Mark Brown
2019-10-17 14:18 ` [PATCH 6/7] spi: atmel: Improve and fix GPIO CS usage Gregory CLEMENT
2019-10-18 18:07 ` Applied "spi: atmel: Improve and fix GPIO CS usage" to the spi tree Mark Brown
2019-10-17 14:18 ` [PATCH 7/7] spi: atmel: Improve CS0 case support on AT91RM9200 Gregory CLEMENT
2019-10-18 18:07 ` Applied "spi: atmel: Improve CS0 case support on AT91RM9200" to the spi tree Mark Brown
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