[PATCH V2 1/5] spi: fspi: enable fspi on imx8qxp and imx8mm

[PATCH V2 1/5] spi: fspi: enable fspi on imx8qxp and imx8mm

[Adam Ford]

From: Han Xu <han.xu-3arQi8VN3Tc@public.gmane.org>

Pull in this patch from NXP's upstream repo to
enable fspi on imx8qxp and imx8mm

Signed-off-by: Han Xu <han.xu-3arQi8VN3Tc@public.gmane.org>
Signed-off-by: Adam Ford <aford173-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
V2: Reorder s-o-b lines to give credit in proper order.

diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 8c5084a3a617..00c7899428a1 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -324,6 +324,22 @@ static const struct nxp_fspi_devtype_data lx2160a_data = {
 	.little_endian = true,  /* little-endian    */
 };
 
+static const struct nxp_fspi_devtype_data imx8mm_data = {
+	.rxfifo = SZ_512,       /* (64  * 64 bits)  */
+	.txfifo = SZ_1K,        /* (128 * 64 bits)  */
+	.ahb_buf_size = SZ_2K,  /* (256 * 64 bits)  */
+	.quirks = 0,
+	.little_endian = true,  /* little-endian    */
+};
+
+static const struct nxp_fspi_devtype_data imx8qxp_data = {
+	.rxfifo = SZ_512,       /* (64  * 64 bits)  */
+	.txfifo = SZ_1K,        /* (128 * 64 bits)  */
+	.ahb_buf_size = SZ_2K,  /* (256 * 64 bits)  */
+	.quirks = 0,
+	.little_endian = true,  /* little-endian    */
+};
+
 struct nxp_fspi {
 	void __iomem *iobase;
 	void __iomem *ahb_addr;
@@ -1076,6 +1092,8 @@ static int nxp_fspi_resume(struct device *dev)
 
 static const struct of_device_id nxp_fspi_dt_ids[] = {
 	{ .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, },
+	{ .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, },
+	{ .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids);
-- 
2.24.0

[PATCH V2 2/5] spi: fspi: dynamically alloc AHB memory

[Adam Ford]

From: Han Xu <han.xu-3arQi8VN3Tc@public.gmane.org>

Apply patch from NXP upstream repo to
dynamically allocate AHB memory as needed.

Signed-off-by: Han Xu <han.xu-3arQi8VN3Tc@public.gmane.org>
Signed-off-by: Adam Ford <aford173-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
V2: Reorder s-o-b lines to give credit in proper order.

diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 00c7899428a1..23abf5ae318e 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -307,6 +307,7 @@
 
 #define POLL_TOUT		5000
 #define NXP_FSPI_MAX_CHIPSELECT		4
+#define NXP_FSPI_MIN_IOMAP	SZ_4M
 
 struct nxp_fspi_devtype_data {
 	unsigned int rxfifo;
@@ -345,6 +346,8 @@ struct nxp_fspi {
 	void __iomem *ahb_addr;
 	u32 memmap_phy;
 	u32 memmap_phy_size;
+	u32 memmap_start;
+	u32 memmap_len;
 	struct clk *clk, *clk_en;
 	struct device *dev;
 	struct completion c;
@@ -657,12 +660,35 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi)
 	f->selected = spi->chip_select;
 }
 
-static void nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
+static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
 {
+	u32 start = op->addr.val;
 	u32 len = op->data.nbytes;
 
+	/* if necessary, ioremap before AHB read */
+	if ((!f->ahb_addr) || start < f->memmap_start ||
+	     start + len > f->memmap_start + f->memmap_len) {
+		if (f->ahb_addr)
+			iounmap(f->ahb_addr);
+
+		f->memmap_start = start;
+		f->memmap_len = len > NXP_FSPI_MIN_IOMAP ?
+				len : NXP_FSPI_MIN_IOMAP;
+
+		f->ahb_addr = ioremap_wc(f->memmap_phy + f->memmap_start,
+					 f->memmap_len);
+
+		if (!f->ahb_addr) {
+			dev_err(f->dev, "failed to alloc memory\n");
+			return -ENOMEM;
+		}
+	}
+
 	/* Read out the data directly from the AHB buffer. */
-	memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), len);
+	memcpy_fromio(op->data.buf.in,
+		      f->ahb_addr + start - f->memmap_start, len);
+
+	return 0;
 }
 
 static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
@@ -822,7 +848,7 @@ static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
 	 */
 	if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
 	    op->data.dir == SPI_MEM_DATA_IN) {
-		nxp_fspi_read_ahb(f, op);
+		err = nxp_fspi_read_ahb(f, op);
 	} else {
 		if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
 			nxp_fspi_fill_txfifo(f, op);
@@ -992,9 +1018,8 @@ static int nxp_fspi_probe(struct platform_device *pdev)
 
 	/* find the resources - controller memory mapped space */
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fspi_mmap");
-	f->ahb_addr = devm_ioremap_resource(dev, res);
-	if (IS_ERR(f->ahb_addr)) {
-		ret = PTR_ERR(f->ahb_addr);
+	if (IS_ERR(res)) {
+		ret = PTR_ERR(res);
 		goto err_put_ctrl;
 	}
 
@@ -1073,6 +1098,9 @@ static int nxp_fspi_remove(struct platform_device *pdev)
 
 	mutex_destroy(&f->lock);
 
+	if (f->ahb_addr)
+		iounmap(f->ahb_addr);
+
 	return 0;
 }
 
-- 
2.24.0

Re: [PATCH V2 2/5] spi: fspi: dynamically alloc AHB memory

[Fabio Estevam]

On Sun, Feb 2, 2020 at 10:00 AM Adam Ford <aford173-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>
> From: Han Xu <han.xu-3arQi8VN3Tc@public.gmane.org>
>
> Apply patch from NXP upstream repo to
> dynamically allocate AHB memory as needed.

The commit log could be improved here. What is the motivation for doing this?

> +               if (!f->ahb_addr) {
> +                       dev_err(f->dev, "failed to alloc memory\n");

There is no need for this error message as the MM core will take care of it.

Re: [PATCH V2 2/5] spi: fspi: dynamically alloc AHB memory

[Adam Ford]

On Sun, Feb 2, 2020 at 10:39 AM Fabio Estevam <festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>
> On Sun, Feb 2, 2020 at 10:00 AM Adam Ford <aford173-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> >
> > From: Han Xu <han.xu-3arQi8VN3Tc@public.gmane.org>
> >
> > Apply patch from NXP upstream repo to
> > dynamically allocate AHB memory as needed.
>
> The commit log could be improved here. What is the motivation for doing this?

My motivation is to get the flexspi on the i.MX8MM to work, and I did
a list of the patches applied on the NXP branch to see what was
applied on top of their 4.19 kernel and this patch series generated
from that list.  Most of the NXP commits are one-line commits, and I
don't know the motivation for what's happening.  NXP did it, and I
know it works on the Flexspi driver.

Maybe Han Xu can comment, since it's really his patch.


adam
>
> > +               if (!f->ahb_addr) {
> > +                       dev_err(f->dev, "failed to alloc memory\n");
>
> There is no need for this error message as the MM core will take care of it.

Re: [PATCH V2 2/5] spi: fspi: dynamically alloc AHB memory

[Mark Brown]

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On Mon, Feb 03, 2020 at 04:53:34AM -0600, Adam Ford wrote:

> My motivation is to get the flexspi on the i.MX8MM to work, and I did
> a list of the patches applied on the NXP branch to see what was
> applied on top of their 4.19 kernel and this patch series generated
> from that list.  Most of the NXP commits are one-line commits, and I
> don't know the motivation for what's happening.  NXP did it, and I
> know it works on the Flexspi driver.

Adding new compatibles and so on seems fine but the patches making
random changes without explanation like the one for octal mode I just
replied to are more worrying, do they work with older versions of the IP
or in all use cases for example?  I'd suggest cutting the initial patch
series down to the bare minimum needed to get things working and then
building on top of that if that's not already been done.

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Re: [PATCH V2 2/5] spi: fspi: dynamically alloc AHB memory

[Adam Ford]

On Wed, Feb 12, 2020 at 6:07 AM Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>
> On Mon, Feb 03, 2020 at 04:53:34AM -0600, Adam Ford wrote:
>
> > My motivation is to get the flexspi on the i.MX8MM to work, and I did
> > a list of the patches applied on the NXP branch to see what was
> > applied on top of their 4.19 kernel and this patch series generated
> > from that list.  Most of the NXP commits are one-line commits, and I
> > don't know the motivation for what's happening.  NXP did it, and I
> > know it works on the Flexspi driver.
>
> Adding new compatibles and so on seems fine but the patches making
> random changes without explanation like the one for octal mode I just
> replied to are more worrying, do they work with older versions of the IP
> or in all use cases for example?  I'd suggest cutting the initial patch
> series down to the bare minimum needed to get things working and then
> building on top of that if that's not already been done.

The original author was copied on the initial commit.  I literally
generated the patch from NXP's branch,  added my notes, and pushed
them to the mailing lists after testing them on the  the Linux master
branch.   I am a bit disappointed that NXP's author hasn't responded
to any of the comments or feedback.  NXP knows their hardware and
better understands the details as to what is happening and why.  In
any case,  I'll try to scale the patch series back to just enough to
get it working on the i.MX8M Mini.  I'll expand a bit on the commit
message based on what I've learned about the various in-implemented
quirks and send a V2 series.

adam

Re: [PATCH V2 2/5] spi: fspi: dynamically alloc AHB memory

[Mark Brown]

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On Wed, Feb 12, 2020 at 07:08:49AM -0600, Adam Ford wrote:

> The original author was copied on the initial commit.  I literally
> generated the patch from NXP's branch,  added my notes, and pushed
> them to the mailing lists after testing them on the  the Linux master
> branch.   I am a bit disappointed that NXP's author hasn't responded
> to any of the comments or feedback.  NXP knows their hardware and

Bear in mind that it's been the spring festival and there's been quite a
bit of delay in getting back to work in China resulting from coronavirus
stuff so hopefully it's just a delay in replying.

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RE: [EXT] Re: [PATCH V2 2/5] spi: fspi: dynamically alloc AHB memory

[Han Xu]

> -----Original Message-----
> From: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Sent: Thursday, February 13, 2020 12:46 PM
> To: Adam Ford <aford173-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Fabio Estevam <festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>; linux-spi <linux-spi-u79uwXL29TasMV2rI37PzA@public.gmane.orgorg>;
> Han Xu <han.xu-3arQi8VN3Tc@public.gmane.org>; Yogesh Gaur <yogeshgaur.83-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>; Ashish
> Kumar <ashish.kumar-3arQi8VN3Tc@public.gmane.org>; Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; Mark
> Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>; Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; Sascha
> Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>; Pengutronix Kernel Team
> <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>; dl-linux-imx <linux-imx-3arQi8VN3Tc@public.gmane.org>; open list:OPEN
> FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; linux-kernel <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>;
> moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE <linux-arm-
> kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
> Subject: [EXT] Re: [PATCH V2 2/5] spi: fspi: dynamically alloc AHB memory
> 
> On Wed, Feb 12, 2020 at 07:08:49AM -0600, Adam Ford wrote:
> 
> > The original author was copied on the initial commit.  I literally
> > generated the patch from NXP's branch,  added my notes, and pushed
> > them to the mailing lists after testing them on the  the Linux master
> > branch.   I am a bit disappointed that NXP's author hasn't responded
> > to any of the comments or feedback.  NXP knows their hardware and
> 
> Bear in mind that it's been the spring festival and there's been quite a bit of delay
> in getting back to work in China resulting from coronavirus stuff so hopefully it's
> just a delay in replying.

The FSPI is a shared IP with other NXP BU. We are debugging an issue may related to this patch. I will resend the patch set after the root cause found.

[PATCH V2 4/5] dt-bindings: spi: spi-nxp-fspi: Add support for imx8mm, imx8qxp

[Adam Ford]

Add support for nxp,imx8qxp-fspi and nxp,imx8mm-fspi do the bindings
document.

Signed-off-by: Adam Ford <aford173-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
V2: No change

diff --git a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
index 2cd67eb727d4..7ac60d9fe357 100644
--- a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
@@ -2,6 +2,9 @@
 
 Required properties:
   - compatible : Should be "nxp,lx2160a-fspi"
+			    "nxp,imx8qxp-fspi"
+			    "nxp,imx8mm-fspi"
+
   - reg :        First contains the register location and length,
                  Second contains the memory mapping address and length
   - reg-names :  Should contain the resource reg names:
-- 
2.24.0

Re: [PATCH V2 4/5] dt-bindings: spi: spi-nxp-fspi: Add support for imx8mm, imx8qxp

[Rob Herring]

On Sun, Feb 02, 2020 at 06:59:49AM -0600, Adam Ford wrote:
> Add support for nxp,imx8qxp-fspi and nxp,imx8mm-fspi do the bindings

s/do/to/

> document.
> 
> Signed-off-by: Adam Ford <aford173-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> V2: No change
> 
> diff --git a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
> index 2cd67eb727d4..7ac60d9fe357 100644
> --- a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
> +++ b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
> @@ -2,6 +2,9 @@
>  
>  Required properties:
>    - compatible : Should be "nxp,lx2160a-fspi"
> +			    "nxp,imx8qxp-fspi"
> +			    "nxp,imx8mm-fspi"

All 3 are different and no compatibility?

> +
>    - reg :        First contains the register location and length,
>                   Second contains the memory mapping address and length
>    - reg-names :  Should contain the resource reg names:
> -- 
> 2.24.0
> 

Re: [PATCH V2 4/5] dt-bindings: spi: spi-nxp-fspi: Add support for imx8mm, imx8qxp

[Adam Ford]

On Thu, Feb 6, 2020 at 2:46 PM Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>
> On Sun, Feb 02, 2020 at 06:59:49AM -0600, Adam Ford wrote:
> > Add support for nxp,imx8qxp-fspi and nxp,imx8mm-fspi do the bindings
>
> s/do/to/

Oops.  Thanks for catching that.

>
> > document.
> >
> > Signed-off-by: Adam Ford <aford173-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > ---
> > V2: No change
> >
> > diff --git a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
> > index 2cd67eb727d4..7ac60d9fe357 100644
> > --- a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
> > +++ b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
> > @@ -2,6 +2,9 @@
> >
> >  Required properties:
> >    - compatible : Should be "nxp,lx2160a-fspi"
> > +                         "nxp,imx8qxp-fspi"
> > +                         "nxp,imx8mm-fspi"
>
> All 3 are different and no compatibility?

This was all based on a series from NXP's repo where they have some
data tables all associated to the various compatible entries, and they
created a place holder for quirks.  Based on an older NXP repo, it
seems like there might be some quirks associated to the different
families, but the newer repo where I got this patch series didn't
implement them, however, it's possible the quirks may enhance
functionality later. If that's true, I think this is the best solution
for future enhancements without having to change the compatibility
names down the road.  Maybe someone from NXP can comment?  I am just
trying to help push things upstream so we can support QSPI flash.  I
would prefer to keep them separate for now, because we might have
these improvements later. However, I'll do what you request.  Do you
want me to drop the additional compatible flags and just use the
original, or create a new one that's a bit more generic?

adam


adam
>
> > +
> >    - reg :        First contains the register location and length,
> >                   Second contains the memory mapping address and length
> >    - reg-names :  Should contain the resource reg names:
> > --
> > 2.24.0
> >

Re: [PATCH V2 4/5] dt-bindings: spi: spi-nxp-fspi: Add support for imx8mm, imx8qxp

[Rob Herring]

On Tue, Feb 11, 2020 at 4:49 AM Adam Ford <aford173-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>
> On Thu, Feb 6, 2020 at 2:46 PM Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> >
> > On Sun, Feb 02, 2020 at 06:59:49AM -0600, Adam Ford wrote:
> > > Add support for nxp,imx8qxp-fspi and nxp,imx8mm-fspi do the bindings
> >
> > s/do/to/
>
> Oops.  Thanks for catching that.
>
> >
> > > document.
> > >
> > > Signed-off-by: Adam Ford <aford173-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > > ---
> > > V2: No change
> > >
> > > diff --git a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
> > > index 2cd67eb727d4..7ac60d9fe357 100644
> > > --- a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
> > > +++ b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
> > > @@ -2,6 +2,9 @@
> > >
> > >  Required properties:
> > >    - compatible : Should be "nxp,lx2160a-fspi"
> > > +                         "nxp,imx8qxp-fspi"
> > > +                         "nxp,imx8mm-fspi"
> >
> > All 3 are different and no compatibility?
>
> This was all based on a series from NXP's repo where they have some
> data tables all associated to the various compatible entries, and they
> created a place holder for quirks.  Based on an older NXP repo, it
> seems like there might be some quirks associated to the different
> families, but the newer repo where I got this patch series didn't
> implement them, however, it's possible the quirks may enhance
> functionality later. If that's true, I think this is the best solution
> for future enhancements without having to change the compatibility
> names down the road.  Maybe someone from NXP can comment?  I am just
> trying to help push things upstream so we can support QSPI flash.  I
> would prefer to keep them separate for now, because we might have
> these improvements later. However, I'll do what you request.  Do you
> want me to drop the additional compatible flags and just use the
> original, or create a new one that's a bit more generic?

Neither.

If you already know that they have differences, then as-is is fine.

If they are believed to be 'the same', then you do:

compatible = "nxp,imx8qxp-fspi", "nxp,imx8mm-fspi";

assuming i.MX8MM was the first version.

This allows a MX8QXP to work without OS changes if the driver already
supports the previous chip. And if any quirks are found, then the OS
can handle them without a DT change.

Rob

[PATCH V2 5/5] arm64: dts: enable fspi in imx8mm dts

[Adam Ford]

Pull in upstream patch from NXP repo to:
enable fspi in imx8mm DT file

Signed-off-by: Han Xu <han.xu-3arQi8VN3Tc@public.gmane.org>
Signed-off-by: Adam Ford <aford173-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
V2: Reorder s-o-b lines to give credit in proper order.

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 1e5e11592f7b..679769fe6cab 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -558,7 +558,21 @@ aips3: bus@30800000 {
 			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0x30800000 0x30800000 0x400000>;
+			ranges = <0x30800000 0x30800000 0x400000>,
+				 <0x8000000 0x8000000 0x10000000>;
+
+			flexspi: spi@30bb0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "nxp,imx8mm-fspi";
+				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
+				reg-names = "fspi_base", "fspi_mmap";
+				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
+					 <&clk IMX8MM_CLK_QSPI_ROOT>;
+				clock-names = "fspi", "fspi_en";
+				status = "disabled";
+			};
 
 			ecspi1: spi@30820000 {
 				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
-- 
2.24.0

Re: [PATCH V2 5/5] arm64: dts: enable fspi in imx8mm dts

[Shawn Guo]

On Sun, Feb 02, 2020 at 06:59:50AM -0600, Adam Ford wrote:
> Pull in upstream patch from NXP repo to:
> enable fspi in imx8mm DT file
> 
> Signed-off-by: Han Xu <han.xu-3arQi8VN3Tc@public.gmane.org>
> Signed-off-by: Adam Ford <aford173-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> V2: Reorder s-o-b lines to give credit in proper order.
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 1e5e11592f7b..679769fe6cab 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -558,7 +558,21 @@ aips3: bus@30800000 {
>  			compatible = "simple-bus";
>  			#address-cells = <1>;
>  			#size-cells = <1>;
> -			ranges = <0x30800000 0x30800000 0x400000>;
> +			ranges = <0x30800000 0x30800000 0x400000>,
> +				 <0x8000000 0x8000000 0x10000000>;
> +
> +			flexspi: spi@30bb0000 {

Keep the node sort in unit-address.

Shawn

> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "nxp,imx8mm-fspi";
> +				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
> +				reg-names = "fspi_base", "fspi_mmap";
> +				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
> +					 <&clk IMX8MM_CLK_QSPI_ROOT>;
> +				clock-names = "fspi", "fspi_en";
> +				status = "disabled";
> +			};
>  
>  			ecspi1: spi@30820000 {
>  				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
> -- 
> 2.24.0
> 

[PATCH V2 3/5] spi: spi-nxp-fspi: Enable the Octal Mode in MCR0

[Adam Ford]

From: Han Xu <han.xu@nxp.com>

Apply patch from NXP upstream repo to
Enable the octal combination mode in MCR0

Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
---
V2: Reorder s-o-b lines to give credit in proper order.

diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 23abf5ae318e..019f40e2917c 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -913,8 +913,9 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f)
 	fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
 
 	/* enable module */
-	fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | FSPI_MCR0_IP_TIMEOUT(0xFF),
-		 base + FSPI_MCR0);
+	fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) |
+		    FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32) FSPI_MCR0_OCTCOMB_EN,
+		    base + FSPI_MCR0);
 
 	/*
 	 * Disable same device enable bit and configure all slave devices
-- 
2.24.0

Re: [PATCH V2 3/5] spi: spi-nxp-fspi: Enable the Octal Mode in MCR0

[Mark Brown]

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On Sun, Feb 02, 2020 at 06:59:48AM -0600, Adam Ford wrote:
> From: Han Xu <han.xu-3arQi8VN3Tc@public.gmane.org>
> 
> Apply patch from NXP upstream repo to
> Enable the octal combination mode in MCR0

Why?

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