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* (unknown)
@ 2020-02-11 22:34 ` Rajat Jain
       [not found]   ` <20200211223400.107604-1-rajatja-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
  2020-02-26 19:00   ` Patchwork summary for: spi-devel-general patchwork-bot+linux-spi-DgEjT+Ai2ygdnm+yROfE0A
  0 siblings, 2 replies; 14+ messages in thread
From: Rajat Jain @ 2020-02-11 22:34 UTC (permalink / raw)
  To: Daniel Mack, Haojian Zhuang, Robert Jarzmik, Mark Brown,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-spi-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA
  Cc: Evan Green, rajatja-hpIqsD4AKlfQT0dZR+AlfA,
	rajatxjain-Re5JQEeQqe8AvxtiuMwx3w,
	evgreen-hpIqsD4AKlfQT0dZR+AlfA,
	shobhit.srivastava-ral2JQCrhuEAvxtiuMwx3w,
	porselvan.muthukrishnan-ral2JQCrhuEAvxtiuMwx3w

From: Evan Green <evgreen-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>

Date: Wed, 29 Jan 2020 13:54:16 -0800
Subject: [PATCH] spi: pxa2xx: Add CS control clock quirk

In some circumstances on Intel LPSS controllers, toggling the LPSS
CS control register doesn't actually cause the CS line to toggle.
This seems to be failure of dynamic clock gating that occurs after
going through a suspend/resume transition, where the controller
is sent through a reset transition. This ruins SPI transactions
that either rely on delay_usecs, or toggle the CS line without
sending data.

Whenever CS is toggled, momentarily set the clock gating register
to "Force On" to poke the controller into acting on CS.

Signed-off-by: Evan Green <evgreen-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Rajat Jain <rajatja-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
---
 drivers/spi/spi-pxa2xx.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 4c7a71f0fb3e..2e318158fca9 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -70,6 +70,10 @@ MODULE_ALIAS("platform:pxa2xx-spi");
 #define LPSS_CAPS_CS_EN_SHIFT			9
 #define LPSS_CAPS_CS_EN_MASK			(0xf << LPSS_CAPS_CS_EN_SHIFT)
 
+#define LPSS_PRIV_CLOCK_GATE 0x38
+#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
+#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
+
 struct lpss_config {
 	/* LPSS offset from drv_data->ioaddr */
 	unsigned offset;
@@ -86,6 +90,8 @@ struct lpss_config {
 	unsigned cs_sel_shift;
 	unsigned cs_sel_mask;
 	unsigned cs_num;
+	/* Quirks */
+	unsigned cs_clk_stays_gated : 1;
 };
 
 /* Keep these sorted with enum pxa_ssp_type */
@@ -156,6 +162,7 @@ static const struct lpss_config lpss_platforms[] = {
 		.tx_threshold_hi = 56,
 		.cs_sel_shift = 8,
 		.cs_sel_mask = 3 << 8,
+		.cs_clk_stays_gated = true,
 	},
 };
 
@@ -383,6 +390,22 @@ static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
 	else
 		value |= LPSS_CS_CONTROL_CS_HIGH;
 	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
+	if (config->cs_clk_stays_gated) {
+		u32 clkgate;
+
+		/*
+		 * Changing CS alone when dynamic clock gating is on won't
+		 * actually flip CS at that time. This ruins SPI transfers
+		 * that specify delays, or have no data. Toggle the clock mode
+		 * to force on briefly to poke the CS pin to move.
+		 */
+		clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
+		value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
+			LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
+
+		__lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
+		__lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
+	}
 }
 
 static void cs_assert(struct spi_device *spi)
-- 
2.25.0.225.g125e21ebc7-goog

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH] spi: pxa2xx: Add CS control clock quirk
@ 2020-02-11 22:37 Rajat Jain
  2020-02-11 22:34 ` (unknown) Rajat Jain
  0 siblings, 1 reply; 14+ messages in thread
From: Rajat Jain @ 2020-02-11 22:37 UTC (permalink / raw)
  To: Daniel Mack, Haojian Zhuang, Robert Jarzmik, Mark Brown,
	linux-arm-kernel, linux-spi, linux-kernel
  Cc: Evan Green, rajatja, rajatxjain, evgreen, shobhit.srivastava,
	porselvan.muthukrishnan

From: Evan Green <evgreen@chromium.org>

In some circumstances on Intel LPSS controllers, toggling the LPSS
CS control register doesn't actually cause the CS line to toggle.
This seems to be failure of dynamic clock gating that occurs after
going through a suspend/resume transition, where the controller
is sent through a reset transition. This ruins SPI transactions
that either rely on delay_usecs, or toggle the CS line without
sending data.

Whenever CS is toggled, momentarily set the clock gating register
to "Force On" to poke the controller into acting on CS.

Signed-off-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Rajat Jain <rajatja@google.com>
---
 drivers/spi/spi-pxa2xx.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 4c7a71f0fb3e..2e318158fca9 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -70,6 +70,10 @@ MODULE_ALIAS("platform:pxa2xx-spi");
 #define LPSS_CAPS_CS_EN_SHIFT			9
 #define LPSS_CAPS_CS_EN_MASK			(0xf << LPSS_CAPS_CS_EN_SHIFT)
 
+#define LPSS_PRIV_CLOCK_GATE 0x38
+#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
+#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
+
 struct lpss_config {
 	/* LPSS offset from drv_data->ioaddr */
 	unsigned offset;
@@ -86,6 +90,8 @@ struct lpss_config {
 	unsigned cs_sel_shift;
 	unsigned cs_sel_mask;
 	unsigned cs_num;
+	/* Quirks */
+	unsigned cs_clk_stays_gated : 1;
 };
 
 /* Keep these sorted with enum pxa_ssp_type */
@@ -156,6 +162,7 @@ static const struct lpss_config lpss_platforms[] = {
 		.tx_threshold_hi = 56,
 		.cs_sel_shift = 8,
 		.cs_sel_mask = 3 << 8,
+		.cs_clk_stays_gated = true,
 	},
 };
 
@@ -383,6 +390,22 @@ static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
 	else
 		value |= LPSS_CS_CONTROL_CS_HIGH;
 	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
+	if (config->cs_clk_stays_gated) {
+		u32 clkgate;
+
+		/*
+		 * Changing CS alone when dynamic clock gating is on won't
+		 * actually flip CS at that time. This ruins SPI transfers
+		 * that specify delays, or have no data. Toggle the clock mode
+		 * to force on briefly to poke the CS pin to move.
+		 */
+		clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
+		value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
+			LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
+
+		__lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
+		__lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
+	}
 }
 
 static void cs_assert(struct spi_device *spi)
-- 
2.25.0.225.g125e21ebc7-goog

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re:
       [not found]   ` <20200211223400.107604-1-rajatja-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
@ 2020-02-12  9:30     ` Jarkko Nikula
       [not found]       ` <b3397374-0cb8-cf6c-0555-34541a1c108c-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
  0 siblings, 1 reply; 14+ messages in thread
From: Jarkko Nikula @ 2020-02-12  9:30 UTC (permalink / raw)
  To: Rajat Jain, Daniel Mack, Haojian Zhuang, Robert Jarzmik,
	Mark Brown, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-spi-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA
  Cc: Evan Green, rajatxjain-Re5JQEeQqe8AvxtiuMwx3w,
	evgreen-hpIqsD4AKlfQT0dZR+AlfA,
	shobhit.srivastava-ral2JQCrhuEAvxtiuMwx3w,
	porselvan.muthukrishnan-ral2JQCrhuEAvxtiuMwx3w, Andy Shevchenko

Hi

+ Andy

On 2/12/20 12:34 AM, Rajat Jain wrote:
> From: Evan Green <evgreen-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> 
> Date: Wed, 29 Jan 2020 13:54:16 -0800
> Subject: [PATCH] spi: pxa2xx: Add CS control clock quirk
> 
This patch subject is missing from mail subject.

> In some circumstances on Intel LPSS controllers, toggling the LPSS
> CS control register doesn't actually cause the CS line to toggle.
> This seems to be failure of dynamic clock gating that occurs after
> going through a suspend/resume transition, where the controller
> is sent through a reset transition. This ruins SPI transactions
> that either rely on delay_usecs, or toggle the CS line without
> sending data.
> 
> Whenever CS is toggled, momentarily set the clock gating register
> to "Force On" to poke the controller into acting on CS.
> 
Could you share the test case how to trigger this? What's the platform 
here? I'd like to check does this reproduce on other Intel LPSS 
platforms so is there need to add quirk for them too.

> Signed-off-by: Evan Green <evgreen-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> Signed-off-by: Rajat Jain <rajatja-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
> ---
>   drivers/spi/spi-pxa2xx.c | 23 +++++++++++++++++++++++
>   1 file changed, 23 insertions(+)
> 
> diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
> index 4c7a71f0fb3e..2e318158fca9 100644
> --- a/drivers/spi/spi-pxa2xx.c
> +++ b/drivers/spi/spi-pxa2xx.c
> @@ -70,6 +70,10 @@ MODULE_ALIAS("platform:pxa2xx-spi");
>   #define LPSS_CAPS_CS_EN_SHIFT			9
>   #define LPSS_CAPS_CS_EN_MASK			(0xf << LPSS_CAPS_CS_EN_SHIFT)
>   
> +#define LPSS_PRIV_CLOCK_GATE 0x38
> +#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
> +#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
> +
>   struct lpss_config {
>   	/* LPSS offset from drv_data->ioaddr */
>   	unsigned offset;
> @@ -86,6 +90,8 @@ struct lpss_config {
>   	unsigned cs_sel_shift;
>   	unsigned cs_sel_mask;
>   	unsigned cs_num;
> +	/* Quirks */
> +	unsigned cs_clk_stays_gated : 1;
>   };
>   
>   /* Keep these sorted with enum pxa_ssp_type */
> @@ -156,6 +162,7 @@ static const struct lpss_config lpss_platforms[] = {
>   		.tx_threshold_hi = 56,
>   		.cs_sel_shift = 8,
>   		.cs_sel_mask = 3 << 8,
> +		.cs_clk_stays_gated = true,
>   	},
>   };
>   
> @@ -383,6 +390,22 @@ static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
>   	else
>   		value |= LPSS_CS_CONTROL_CS_HIGH;
>   	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
> +	if (config->cs_clk_stays_gated) {
> +		u32 clkgate;
> +
> +		/*
> +		 * Changing CS alone when dynamic clock gating is on won't
> +		 * actually flip CS at that time. This ruins SPI transfers
> +		 * that specify delays, or have no data. Toggle the clock mode
> +		 * to force on briefly to poke the CS pin to move.
> +		 */
> +		clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
> +		value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
> +			LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
> +
> +		__lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
> +		__lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
> +	}
>   }
>   
I wonder is it enough to have this quick toggling only or is time or 
actually number of clock cycles dependent? Now there is no delay between 
but I'm thinking if it needs certain number cycles does this still work 
when using low ssp_clk rates similar than in commit d0283eb2dbc1 ("spi: 
pxa2xx: Add output control for multiple Intel LPSS chip selects").

I'm thinking can this be done only once after resume and may other LPSS 
blocks need the same? I.e. should this be done in drivers/mfd/intel-lpss.c?

Jarkko

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re:
       [not found]       ` <b3397374-0cb8-cf6c-0555-34541a1c108c-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
@ 2020-02-12 10:24         ` Andy Shevchenko
  0 siblings, 0 replies; 14+ messages in thread
From: Andy Shevchenko @ 2020-02-12 10:24 UTC (permalink / raw)
  To: Jarkko Nikula
  Cc: Rajat Jain, Daniel Mack, Haojian Zhuang, Robert Jarzmik,
	Mark Brown, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-spi-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA, Evan Green,
	rajatxjain-Re5JQEeQqe8AvxtiuMwx3w,
	evgreen-hpIqsD4AKlfQT0dZR+AlfA,
	shobhit.srivastava-ral2JQCrhuEAvxtiuMwx3w,
	porselvan.muthukrishnan-ral2JQCrhuEAvxtiuMwx3w

On Wed, Feb 12, 2020 at 11:30:51AM +0200, Jarkko Nikula wrote:
> On 2/12/20 12:34 AM, Rajat Jain wrote:

> This patch subject is missing from mail subject.

> I'm thinking can this be done only once after resume and may other LPSS
> blocks need the same? I.e. should this be done in drivers/mfd/intel-lpss.c?

On resume we restore the previously saved context, can we be sure that values
we saved during suspend are correct?

If above won't show any issue, it might be best place to have this quirk
applied in intel_lpss_suspend() / intel_lpss_resume() callbacks as Jarkko
suggested.

-- 
With Best Regards,
Andy Shevchenko

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Patchwork summary for: spi-devel-general
  2020-02-11 22:34 ` (unknown) Rajat Jain
       [not found]   ` <20200211223400.107604-1-rajatja-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
@ 2020-02-26 19:00   ` patchwork-bot+linux-spi-DgEjT+Ai2ygdnm+yROfE0A
  1 sibling, 0 replies; 14+ messages in thread
From: patchwork-bot+linux-spi-DgEjT+Ai2ygdnm+yROfE0A @ 2020-02-26 19:00 UTC (permalink / raw)
  To: linux-spi-u79uwXL29TY76Z2rM5mHXA, broonie-DgEjT+Ai2ygdnm+yROfE0A

Hello:

The following patches were marked "accepted", because they were applied to
broonie/spi.git (refs/heads/for-next):

Patch: spi: pxa2xx: Add CS control clock quirk
  Submitter: Rajat Jain <rajatja-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
  Patchwork: https://patchwork.kernel.org/project/spi-devel-general/list/?series=240023

Patch: 
  Submitter: Rajat Jain <rajatja-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
  Patchwork: https://patchwork.kernel.org/project/spi-devel-general/list/?series=240019

Total patches: 2

-- 
Deet-doot-dot, I am a bot.
https://korg.wiki.kernel.org/userdoc/pwbot

^ permalink raw reply	[flat|nested] 14+ messages in thread

* (unknown)
@ 2020-03-09  7:34 Michael J. Weirsky
  0 siblings, 0 replies; 14+ messages in thread
From: Michael J. Weirsky @ 2020-03-09  7:34 UTC (permalink / raw)




-- 
My name is Michael J. Weirsky, I'm an unemployed Handy man , winner of 
$273million Jackpot in March 8, 2019. I donate $1.000.000,00 to you. 
Contact me via email: micjsky-YDxpq3io04c@public.gmane.org for info / claim.
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^ permalink raw reply	[flat|nested] 14+ messages in thread

* (unknown), 
@ 2017-06-25  2:39 bflove1-ntQ8I44N4zM
  0 siblings, 0 replies; 14+ messages in thread
From: bflove1-ntQ8I44N4zM @ 2017-06-25  2:39 UTC (permalink / raw)
  To: linux-spi-u79uwXL29TY76Z2rM5mHXA


[-- Attachment #0: EMAIL_64201799182639_linux-spi.zip --]
[-- Type: application/zip, Size: 3503 bytes --]

^ permalink raw reply	[flat|nested] 14+ messages in thread

* (unknown), 
@ 2017-03-20 19:40 janepatrick00-VmEwxm1hRrAnxqbYAscKCQ
  0 siblings, 0 replies; 14+ messages in thread
From: janepatrick00-VmEwxm1hRrAnxqbYAscKCQ @ 2017-03-20 19:40 UTC (permalink / raw)
  To: Recipients

Hello,
My name is Jane from UK, I came across you email address online, I will like to know more about you , I have a very important reason of contacting you which, I'll tell you in my next mail.
I wait for your reply
--
To unsubscribe from this list: send the line "unsubscribe linux-spi" in
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^ permalink raw reply	[flat|nested] 14+ messages in thread

* (unknown), 
@ 2017-01-22 20:22 bflove1-ntQ8I44N4zM
  0 siblings, 0 replies; 14+ messages in thread
From: bflove1-ntQ8I44N4zM @ 2017-01-22 20:22 UTC (permalink / raw)
  To: linux-spi


[-- Attachment #0: EMAIL_30700_linux-spi.zip --]
[-- Type: application/zip, Size: 15020 bytes --]

^ permalink raw reply	[flat|nested] 14+ messages in thread

* (unknown)
  2017-01-13 10:46   ` [PATCH v3 0/8] " Nicolas Dichtel
@ 2017-01-13 15:36     ` David Howells
  0 siblings, 0 replies; 14+ messages in thread
From: David Howells @ 2017-01-13 15:36 UTC (permalink / raw)
  To: Nicolas Dichtel
  Cc: dhowells, arnd, linux-mips, linux-m68k, linux-ia64, linux-doc,
	alsa-devel, dri-devel, linux-mtd, sparclinux, linux-arch,
	linux-s390, linux-am33-list, linux-c6x-dev, linux-rdma,
	linux-hexagon, linux-sh, linux, coreteam, fcoe-devel, xen-devel,
	linux-snps-arc, linux-media, uclinux-h8-devel, linux-xtensa,
	linux-kbuild, adi-buildroot-devel, linux-

Nicolas Dichtel <nicolas.dichtel@6wind.com> wrote:

> This header file is exported, thus move it to uapi.

Exported how?

> +#ifdef __INT32_TYPE__
> +#undef __INT32_TYPE__
> +#define __INT32_TYPE__		int
> +#endif
> +
> +#ifdef __UINT32_TYPE__
> +#undef __UINT32_TYPE__
> +#define __UINT32_TYPE__	unsigned int
> +#endif
> +
> +#ifdef __UINTPTR_TYPE__
> +#undef __UINTPTR_TYPE__
> +#define __UINTPTR_TYPE__	unsigned long
> +#endif

These weren't defined by the kernel before, so why do we need to define them
now?

Will defining __UINTPTR_TYPE__ cause problems in compiling libboost by
changing the signature on C++ functions that use uintptr_t?

David

^ permalink raw reply	[flat|nested] 14+ messages in thread

* (unknown)
       [not found]                                                                                                     ` <1881200547.147301.1414958000634.JavaMail.yahoo-omb7QOROZBYQkHVbkOd/apOW+3bF1jUfVpNB7YpNyf8@public.gmane.org>
@ 2014-11-02 19:54                                                                                                       ` MRS GRACE MANDA
  0 siblings, 0 replies; 14+ messages in thread
From: MRS GRACE MANDA @ 2014-11-02 19:54 UTC (permalink / raw)



[-- Attachment #1: Type: text/plain, Size: 137 bytes --]






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[-- Attachment #2: Mrs Grace Manda.rtf --]
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* (unknown)
@ 2014-04-21 13:26 Jorge Ventura
  0 siblings, 0 replies; 14+ messages in thread
From: Jorge Ventura @ 2014-04-21 13:26 UTC (permalink / raw)
  To: linux-spi-u79uwXL29TY76Z2rM5mHXA

unsubscribe linux-spi
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* (unknown), 
@ 2012-09-12 20:09 Karicheri, Muralidharan
  0 siblings, 0 replies; 14+ messages in thread
From: Karicheri, Muralidharan @ 2012-09-12 20:09 UTC (permalink / raw)
  To: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f

subscribe spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org

Murali Karicheri
Software Design Engineer

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^ permalink raw reply	[flat|nested] 14+ messages in thread

* (unknown)
@ 2011-03-04 22:34 L'ALTRA DIMENSIONE
  0 siblings, 0 replies; 14+ messages in thread
From: L'ALTRA DIMENSIONE @ 2011-03-04 22:34 UTC (permalink / raw)
  To: spi-devel-general

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What You Don't Know About Data Connectivity CAN Hurt You
This paper provides an overview of data connectivity, details
its effect on application quality, and explores various alternative
solutions. http://p.sf.net/sfu/progress-d2d

^ permalink raw reply	[flat|nested] 14+ messages in thread

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Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-11 22:37 [PATCH] spi: pxa2xx: Add CS control clock quirk Rajat Jain
2020-02-11 22:34 ` (unknown) Rajat Jain
     [not found]   ` <20200211223400.107604-1-rajatja-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
2020-02-12  9:30     ` Jarkko Nikula
     [not found]       ` <b3397374-0cb8-cf6c-0555-34541a1c108c-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2020-02-12 10:24         ` Re: Andy Shevchenko
2020-02-26 19:00   ` Patchwork summary for: spi-devel-general patchwork-bot+linux-spi-DgEjT+Ai2ygdnm+yROfE0A
  -- strict thread matches above, loose matches on Subject: below --
2020-03-09  7:34 (unknown) Michael J. Weirsky
2017-06-25  2:39 (unknown), bflove1-ntQ8I44N4zM
2017-03-20 19:40 (unknown), janepatrick00-VmEwxm1hRrAnxqbYAscKCQ
2017-01-22 20:22 (unknown), bflove1-ntQ8I44N4zM
2017-01-13 10:46 [PATCH v3 1/8] arm: put types.h in uapi Nicolas Dichtel
2017-01-09 11:33 ` [PATCH v2 0/7] uapi: export all headers under uapi directories Arnd Bergmann
2017-01-13 10:46   ` [PATCH v3 0/8] " Nicolas Dichtel
2017-01-13 15:36     ` (unknown) David Howells
     [not found] <1570038211.167595.1414613146892.JavaMail.yahoo@jws10056.mail.ne1.yahoo.com>
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     [not found]                                                                                                   ` <1454491902.178612.1414615875076.JavaMail.yahoo@jws100209.mail.ne1.yahoo.com>
     [not found]                                                                                                     ` <1881200547.147301.1414958000634.JavaMail.yahoo-omb7QOROZBYQkHVbkOd/apOW+3bF1jUfVpNB7YpNyf8@public.gmane.org>
2014-11-02 19:54                                                                                                       ` (unknown) MRS GRACE MANDA
2014-04-21 13:26 (unknown) Jorge Ventura
2012-09-12 20:09 (unknown), Karicheri, Muralidharan
2011-03-04 22:34 (unknown) L'ALTRA DIMENSIONE

Linux-SPI Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-spi/0 linux-spi/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-spi linux-spi/ https://lore.kernel.org/linux-spi \
		linux-spi@vger.kernel.org
	public-inbox-index linux-spi

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-spi


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git