Execute spi transfers inside FIQ (NMI) or panic

Execute spi transfers inside FIQ (NMI) or panic

[Herbrechtsmeier Dr.-Ing. , Stefan]

Hi,

would it be acceptable to add an additional function to the struct 
spi_controller which handle a transfer inside a NMI context or a panic? 
The new function will transfer data via register polling without any lock.

I must execute an SPI transfer inside a fast interrupt request (FIQ) 
handler or a panic. The FIQ is handled as a non-maskable interrupt 
(NMI). Both the panic and the NMI doesn't support any interrupts.

The background of the request is a non-volatile SPI memory with cached 
date in system memory. The cache must be synchronized back to the SPI 
memory after a power failure or panic.

Regards
   Stefan Herbrechtsmeier

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Re: Execute spi transfers inside FIQ (NMI) or panic

[Mark Brown]

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On Tue, Feb 25, 2020 at 02:27:27PM +0100, Herbrechtsmeier Dr.-Ing. , Stefan wrote:

> would it be acceptable to add an additional function to the struct
> spi_controller which handle a transfer inside a NMI context or a panic? The
> new function will transfer data via register polling without any lock.

That would need to happen as part of a wider change that made it
possible to use such an interface safely and did so, off the top of my
head it's not immediately obvious how one would do that.  You'd need to
get the hardware into a sensible state and then do whatever needs doing
with some cooperation from the client driver in all this which is a bit
of an ask.  It's not a trivial bit of work, but I do see the use case
and it's absolutely valid.

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Re: Execute spi transfers inside FIQ (NMI) or panic

[Herbrechtsmeier Dr.-Ing. , Stefan]

Am 25.02.2020 um 16:53 schrieb Mark Brown:
> On Tue, Feb 25, 2020 at 02:27:27PM +0100, Herbrechtsmeier Dr.-Ing. , Stefan wrote:
>
>> would it be acceptable to add an additional function to the struct
>> spi_controller which handle a transfer inside a NMI context or a panic? The
>> new function will transfer data via register polling without any lock.
> That would need to happen as part of a wider change that made it
> possible to use such an interface safely and did so, off the top of my
> head it's not immediately obvious how one would do that.  You'd need to
> get the hardware into a sensible state and then do whatever needs doing
> with some cooperation from the client driver in all this which is a bit
> of an ask.  It's not a trivial bit of work, but I do see the use case
> and it's absolutely valid.

I see two possible solutions.
a) The complexity is handled inside the client. The client uses the 
controller exclusive and isn’t allowed to use the new panic transfer 
during a normal transfer.
b) The complexity is handled inside the controller. The controller is 
shared between multiple slaves and a panic transfer must abort a running 
transfer.

The first solution keeps the controller driver simple because only a new 
polled transfer is needed. But the prepare and unprepare functions must 
be lock free and power management must be handled lock free to be reused.

The second solution could lead to code duplication because an addition 
panic prepare function must setup the controller from any state and must 
abort a running transfer. Especially the abort could be complex and 
difficult to test. Otherwise the new functionality could be used without 
any constraints.

Re: Execute spi transfers inside FIQ (NMI) or panic

[Mark Brown]

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On Wed, Feb 26, 2020 at 08:36:37AM +0100, Herbrechtsmeier Dr.-Ing. , Stefan wrote:

> I see two possible solutions.
> a) The complexity is handled inside the client. The client uses the
> controller exclusive and isn’t allowed to use the new panic transfer during
> a normal transfer.

Then someone builds a system with two devices attached to a single SPI
controller...  besides, you've got no mechanism for controlling when a
kernel might panic or power might be lost.  I'm not sure a scheme that
relies on being able to control when stuff happens is going to be what
you need.

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Re: Execute spi transfers inside FIQ (NMI) or panic

[Herbrechtsmeier Dr.-Ing. , Stefan]

Am 26.02.2020 um 12:33 schrieb Mark Brown:
> On Wed, Feb 26, 2020 at 08:36:37AM +0100, Herbrechtsmeier Dr.-Ing. , Stefan wrote:
>
>> I see two possible solutions.
>> a) The complexity is handled inside the client. The client uses the
>> controller exclusive and isn’t allowed to use the new panic transfer during
>> a normal transfer.
> Then someone builds a system with two devices attached to a single SPI
> controller...  besides, you've got no mechanism for controlling when a
> kernel might panic or power might be lost.  I'm not sure a scheme that
> relies on being able to control when stuff happens is going to be what
> you need.

In my case this works because I read from the device during probe and 
write to the device during a panic or after power failure. But I 
understand that this isn't a generic solution.