From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98A0CC38A2A for ; Fri, 8 May 2020 18:54:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 78F5024953 for ; Fri, 8 May 2020 18:54:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="EjK6Tpyi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726885AbgEHSyq (ORCPT ); Fri, 8 May 2020 14:54:46 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:57302 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726797AbgEHSyp (ORCPT ); Fri, 8 May 2020 14:54:45 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 048IsMMM109512; Fri, 8 May 2020 13:54:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588964062; bh=vkQhbBYwxsFf8rmPeEJkV1I4wsQY6bW0mKd96d0v7sk=; h=From:To:CC:Subject:Date; b=EjK6Tpyijz9OYnAmGbBNznRY4pyzIG2R19J1RWzP4p5ZjoR6H6gsQhibBd7DGHG6w 4x1xtPLgHOdF3yRTm4+twouWT/XIl/D5jIUtHDBw4xFlYQJnDg919/6X5sYav85PIb 9DOUGqo/pOzw3d1gUgplpqNfyvmidqa+iIpBS+9w= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 048IsLSG117434; Fri, 8 May 2020 13:54:21 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 8 May 2020 13:54:21 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 8 May 2020 13:54:21 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 048IsGpS077355; Fri, 8 May 2020 13:54:17 -0500 From: Vignesh Raghavendra To: Tudor Ambarus , Mark Brown CC: Vignesh Raghavendra , Boris Brezillon , Ramuthevar Vadivel Murugan , , , , , , Subject: [PATCH 0/6] mtd: spi-nor: Move cadence-qaudspi to spi-mem framework Date: Sat, 9 May 2020 00:24:05 +0530 Message-ID: <20200508185411.487-1-vigneshr@ti.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX that intended to move cadence-quadspi driver to spi-mem framework Those patches were trying to accomplish too many things in a single set of patches and need to split into smaller patches. This is reduced version of above series. Changes that are intended to make migration easy are split into separate patches. Patches 1 to 3 drop features that cannot be supported under spi-mem at the moment (backward compatibility is maintained). Patch 4-5 are trivial cleanups. Patch 6 does the actual conversion to spi-mem and patch 7 moves the driver to drivers/spi folder. I have tested both INDAC mode (used by non TI platforms like Altera SoCFPGA) and DAC mode (used by TI platforms) on TI EVMs. Patches to move move bindings over to "Documentation/devicetree/bindings/spi/" directory and also conversion of bindig doc to YAML will be posted separately. Support for Intel platform would follow that. Changes since v12 - Drop intel platform related changes - Drop DT bindings movement to YAML - Split patch moving driver to spi-mem framework framework into multiple patches as suggested by Tudor. v12: https://patchwork.ozlabs.org/project/linux-mtd/list/?series=163343&state=%2A&archive=both Vadivel, I have maintained the additional changes needed on top of this series for Intel platform that were part of your v12 series here (needs cleanup): https://github.com/r-vignesh/linux.git branch: cqspi-mig Please use above branch to test the same. Ramuthevar Vadivel Murugan (2): mtd: spi-nor: Convert cadence-quadspi to use spi-mem framework spi: Move cadence-quadspi driver to drivers/spi/ Vignesh Raghavendra (4): mtd: spi-nor: cadence-quadspi: Drop cdns,is-decoded-cs property mtd: spi-nor: cadence-quadspi: Provide a way to disable DAC mode mtd: spi-nor: cadence-quadspi: Don't initialize rx_dma_complete on failure mtd: spi-nor: cadence-quadspi: Fix error path on failure to acquire reset lines drivers/mtd/spi-nor/controllers/Kconfig | 11 - drivers/mtd/spi-nor/controllers/Makefile | 1 - drivers/spi/Kconfig | 11 + drivers/spi/Makefile | 1 + .../spi-cadence-quadspi.c} | 546 +++++++----------- 5 files changed, 215 insertions(+), 355 deletions(-) rename drivers/{mtd/spi-nor/controllers/cadence-quadspi.c => spi/spi-cadence-quadspi.c} (73%) -- 2.26.2