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From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: Mark Brown <broonie@kernel.org>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>,
	Serge Semin <fancer.lancer@gmail.com>,
	Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>,
	Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>,
	Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Paul Burton <paulburton@kernel.org>,
	Ralf Baechle <ralf@linux-mips.org>, Arnd Bergmann <arnd@arndb.de>,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Rob Herring <robh+dt@kernel.org>, <linux-mips@vger.kernel.org>,
	<devicetree@vger.kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>,
	Jarkko Nikula <jarkko.nikula@linux.intel.com>,
	<linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v3 06/16] spi: dw: Parameterize the DMA Rx/Tx burst length
Date: Thu, 21 May 2020 04:21:56 +0300	[thread overview]
Message-ID: <20200521012206.14472-7-Sergey.Semin@baikalelectronics.ru> (raw)
In-Reply-To: <20200521012206.14472-1-Sergey.Semin@baikalelectronics.ru>

It isn't good to have numeric literals in the code especially if there
are multiple of them and they are related. Let's replace the Tx and Rx
burst level literals with the corresponding constants.

Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org

---

Changelog v3:
- Discard the dws->fifo_len utilization in the Tx FIFO DMA threshold
  setting.
---
 drivers/spi/spi-dw-mid.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index 7bba774885cd..be02fedd87cb 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -19,7 +19,9 @@
 
 #define WAIT_RETRIES	5
 #define RX_BUSY		0
+#define RX_BURST_LEVEL	16
 #define TX_BUSY		1
+#define TX_BURST_LEVEL	16
 
 static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
 {
@@ -214,7 +216,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
 	memset(&txconf, 0, sizeof(txconf));
 	txconf.direction = DMA_MEM_TO_DEV;
 	txconf.dst_addr = dws->dma_addr;
-	txconf.dst_maxburst = 16;
+	txconf.dst_maxburst = TX_BURST_LEVEL;
 	txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	txconf.dst_addr_width = convert_dma_width(dws->n_bytes);
 	txconf.device_fc = false;
@@ -288,7 +290,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
 	memset(&rxconf, 0, sizeof(rxconf));
 	rxconf.direction = DMA_DEV_TO_MEM;
 	rxconf.src_addr = dws->dma_addr;
-	rxconf.src_maxburst = 16;
+	rxconf.src_maxburst = RX_BURST_LEVEL;
 	rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	rxconf.src_addr_width = convert_dma_width(dws->n_bytes);
 	rxconf.device_fc = false;
@@ -313,8 +315,8 @@ static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
 {
 	u16 imr = 0, dma_ctrl = 0;
 
-	dw_writel(dws, DW_SPI_DMARDLR, 0xf);
-	dw_writel(dws, DW_SPI_DMATDLR, 0x10);
+	dw_writel(dws, DW_SPI_DMARDLR, RX_BURST_LEVEL - 1);
+	dw_writel(dws, DW_SPI_DMATDLR, TX_BURST_LEVEL);
 
 	if (xfer->tx_buf) {
 		dma_ctrl |= SPI_DMA_TDMAE;
-- 
2.25.1


  parent reply	other threads:[~2020-05-21  1:23 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-21  1:21 [PATCH v3 00/16] spi: dw: Add generic DW DMA controller support Serge Semin
2020-05-21  1:21 ` [PATCH v3 01/16] spi: dw: Add Tx/Rx finish wait methods to the MID DMA Serge Semin
2020-05-21  3:09   ` Feng Tang
2020-05-21 11:47     ` Serge Semin
2020-05-21 14:55       ` Feng Tang
2020-05-21 15:33         ` Serge Semin
2020-05-22  7:58           ` Feng Tang
2020-05-22 11:32             ` Serge Semin
2020-05-22 12:03               ` Feng Tang
2020-05-22 12:25                 ` Serge Semin
2020-05-21 23:33   ` Serge Semin
2020-05-21  1:21 ` [PATCH v3 02/16] spi: dw: Enable interrupts in accordance with DMA xfer mode Serge Semin
2020-05-21  1:21 ` [PATCH v3 03/16] spi: dw: Discard static DW DMA slave structures Serge Semin
2020-05-21  9:57   ` Andy Shevchenko
     [not found]     ` <20200521121228.aqplh6eftylnys3p@mobilestation>
2020-05-21 12:49       ` Andy Shevchenko
2020-05-21 15:51       ` Mark Brown
2020-05-21 15:56         ` Andy Shevchenko
2020-05-21 15:58         ` Serge Semin
2020-05-21 16:02           ` Andy Shevchenko
2020-05-21 16:39             ` Mark Brown
2020-05-21 16:44               ` Andy Shevchenko
2020-05-21 17:29               ` Serge Semin
2020-05-21  1:21 ` Serge Semin [this message]
2020-05-21 10:23   ` [PATCH v3 06/16] spi: dw: Parameterize the DMA Rx/Tx burst length Andy Shevchenko
2020-05-21  1:21 ` [PATCH v3 07/16] spi: dw: Use DMA max burst to set the request thresholds Serge Semin
2020-05-21 10:49   ` Andy Shevchenko
2020-05-21  1:22 ` [PATCH v3 11/16] spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI Serge Semin
2020-05-21  1:22 ` [PATCH v3 12/16] spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core Serge Semin
2020-05-21  1:22 ` [PATCH v3 14/16] spi: dw: Add DMA support to the DW SPI MMIO driver Serge Semin
2020-05-21  1:22 ` [PATCH v3 16/16] dt-bindings: spi: Convert DW SPI binding to DT schema Serge Semin
     [not found] ` <20200521012206.14472-10-Sergey.Semin@baikalelectronics.ru>
2020-05-21 10:47   ` [PATCH v3 09/16] spi: dw: Add core suffix to the DW APB SSI core source file Andy Shevchenko
2020-05-21 17:46 ` [PATCH v3 00/16] spi: dw: Add generic DW DMA controller support Andy Shevchenko

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