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From: Pratyush Yadav <p.yadav@ti.com>
To: Tudor Ambarus <tudor.ambarus@microchip.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Mark Brown <broonie@kernel.org>,
	Nicolas Ferre <nicolas.ferre@microchip.com>,
	Alexandre Belloni <alexandre.belloni@bootlin.com>,
	Ludovic Desroches <ludovic.desroches@microchip.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Michal Simek <michal.simek@xilinx.com>,
	<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<linux-spi@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>
Cc: Pratyush Yadav <p.yadav@ti.com>, Sekhar Nori <nsekhar@ti.com>,
	Boris Brezillon <boris.brezillon@collabora.com>,
	Mason Yang <masonccyang@mxic.com.tw>
Subject: [PATCH v8 11/19] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode
Date: Sat, 23 May 2020 04:10:34 +0530
Message-ID: <20200522224042.29970-12-p.yadav@ti.com> (raw)
In-Reply-To: <20200522224042.29970-1-p.yadav@ti.com>

Some controllers, like the cadence qspi controller, have trouble reading
only 1 byte in DTR mode. So, do 2 byte reads for SR and FSR commands in
DTR mode, and then discard the second byte.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
 drivers/mtd/spi-nor/core.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 2ad248140b6c..5cb7e391cd29 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -350,7 +350,7 @@ int spi_nor_write_disable(struct spi_nor *nor)
  * spi_nor_read_sr() - Read the Status Register.
  * @nor:	pointer to 'struct spi_nor'.
  * @sr:		pointer to a DMA-able buffer where the value of the
- *              Status Register will be written.
+ *              Status Register will be written. Should be at least 2 bytes.
  *
  * Return: 0 on success, -errno otherwise.
  */
@@ -371,6 +371,11 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
 			op.addr.nbytes = addr_bytes;
 			op.addr.val = 0;
 			op.dummy.nbytes = dummy;
+			/*
+			 * We don't want to read only one byte in DTR mode. So,
+			 * read 2 and then discard the second byte.
+			 */
+			op.data.nbytes = 2;
 		}
 
 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
@@ -394,7 +399,8 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
  * spi_nor_read_fsr() - Read the Flag Status Register.
  * @nor:	pointer to 'struct spi_nor'
  * @fsr:	pointer to a DMA-able buffer where the value of the
- *              Flag Status Register will be written.
+ *              Flag Status Register will be written. Should be at least 2
+ *              bytes.
  *
  * Return: 0 on success, -errno otherwise.
  */
@@ -415,6 +421,11 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
 			op.addr.nbytes = addr_bytes;
 			op.addr.val = 0;
 			op.dummy.nbytes = dummy;
+			/*
+			 * We don't want to read only one byte in DTR mode. So,
+			 * read 2 and then discard the second byte.
+			 */
+			op.data.nbytes = 2;
 		}
 
 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
-- 
2.26.2


  parent reply index

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-22 22:40 [PATCH v8 00/19] mtd: spi-nor: add xSPI Octal DTR support Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 01/19] spi: spi-mem: allow specifying whether an op is DTR or not Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 02/19] spi: spi-mem: allow specifying a command's extension Pratyush Yadav
2020-05-24 20:17   ` Boris Brezillon
2020-05-22 22:40 ` [PATCH v8 03/19] spi: atmel-quadspi: reject DTR ops Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 04/19] spi: spi-mtk-nor: " Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 05/19] mtd: spi-nor: add support for DTR protocol Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 06/19] mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 07/19] mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev D Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 08/19] mtd: spi-nor: sfdp: get command opcode extension type from BFPT Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 09/19] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 10/19] mtd: spi-nor: core: use dummy cycle and address width info from SFDP Pratyush Yadav
2020-05-22 22:40 ` Pratyush Yadav [this message]
2020-05-22 22:40 ` [PATCH v8 12/19] mtd: spi-nor: core: enable octal DTR mode when possible Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 13/19] mtd: spi-nor: sfdp: do not make invalid quad enable fatal Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 14/19] mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 15/19] mtd: spi-nor: core: perform a Soft Reset on shutdown Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 16/19] mtd: spi-nor: core: disable Octal DTR mode on suspend Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 17/19] mtd: spi-nor: core: expose spi_nor_default_setup() in core.h Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 18/19] mtd: spi-nor: spansion: add support for Cypress Semper flash Pratyush Yadav
2020-05-22 22:40 ` [PATCH v8 19/19] mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode Pratyush Yadav

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