From: Pratyush Yadav <me@yadavpratyush.com>
To: Tudor.Ambarus@microchip.com
Cc: p.yadav@ti.com, miquel.raynal@bootlin.com, richard@nod.at,
vigneshr@ti.com, broonie@kernel.org, Nicolas.Ferre@microchip.com,
alexandre.belloni@bootlin.com, Ludovic.Desroches@microchip.com,
matthias.bgg@gmail.com, michal.simek@xilinx.com,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
boris.brezillon@collabora.com, nsekhar@ti.com
Subject: Re: [PATCH v10 13/17] mtd: spi-nor: core: perform a Soft Reset on shutdown
Date: Mon, 20 Jul 2020 21:41:23 +0530 [thread overview]
Message-ID: <20200720161123.dth4rzziidpx5pmb@yadavpratyush.com> (raw)
In-Reply-To: <ccc128f1-2e7b-e64f-c958-ad5cc272085a@microchip.com>
Hi Tudor,
On 08/07/20 04:10PM, Tudor.Ambarus@microchip.com wrote:
> On 6/23/20 9:30 PM, Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Perform a Soft Reset on shutdown on flashes that support it so that the
> > flash can be reset to its initial state and any configurations made by
> > spi-nor (given that they're only done in volatile registers) will be
> > reset. This will hand back the flash in pristine state for any further
> > operations on it.
> >
> > Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> > ---
> > drivers/mtd/spi-nor/core.c | 42 +++++++++++++++++++++++++++++++++++++
> > include/linux/mtd/spi-nor.h | 2 ++
> > 2 files changed, 44 insertions(+)
> >
> > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> > index 4a1f6b343534..27ad9bab06dc 100644
> > --- a/drivers/mtd/spi-nor/core.c
> > +++ b/drivers/mtd/spi-nor/core.c
> > @@ -40,6 +40,9 @@
> >
> > #define SPI_NOR_MAX_ADDR_WIDTH 4
> >
> > +#define SPI_NOR_SRST_SLEEP_MIN 200
> > +#define SPI_NOR_SRST_SLEEP_MAX 400
> > +
> > /**
> > * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
> > * extension type.
> > @@ -3201,6 +3204,41 @@ static int spi_nor_init(struct spi_nor *nor)
> > return 0;
> > }
> >
> > +static void spi_nor_soft_reset(struct spi_nor *nor)
> > +{
> > + struct spi_mem_op op;
> > + int ret;
> > +
> > + op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 8),
> > + SPI_MEM_OP_NO_DUMMY,
> > + SPI_MEM_OP_NO_ADDR,
> > + SPI_MEM_OP_NO_DATA);
> > + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
> > + ret = spi_mem_exec_op(nor->spimem, &op);
> > + if (ret) {
> > + dev_warn(nor->dev, "Software reset failed: %d\n", ret);
> > + return;
> > + }
> > +
> > + op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 8),
> > + SPI_MEM_OP_NO_DUMMY,
> > + SPI_MEM_OP_NO_ADDR,
> > + SPI_MEM_OP_NO_DATA);
> > + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
> > + ret = spi_mem_exec_op(nor->spimem, &op);
> > + if (ret) {
> > + dev_warn(nor->dev, "Software reset failed: %d\n", ret);
> > + return;
> > + }
> > +
> > + /*
> > + * Software Reset is not instant, and the delay varies from flash to
> > + * flash. Looking at a few flashes, most range somewhere below 100
> > + * microseconds. So, sleep for a range of 200-400 us.
> > + */
> > + usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX);
> > +}
> > +
> > /* mtd resume handler */
> > static void spi_nor_resume(struct mtd_info *mtd)
> > {
> > @@ -3220,6 +3258,10 @@ void spi_nor_restore(struct spi_nor *nor)
> > if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
> > nor->flags & SNOR_F_BROKEN_RESET)
> > nor->params->set_4byte_addr_mode(nor, false);
> > +
> > + if (nor->info->flags & SPI_NOR_OCTAL_DTR_READ &&
>
> Why this limitation? Can't we make the software reset available for all
> the modes?
Because I wrote the function spi_nor_soft_reset() from the perspective
of xSPI support, and the xSPI spec only cares about the 8D-8D-8D version
of the soft reset.
BFPT says we can execute it on 1, 2, 4, or 8 wires depending on the mode
so I guess we can support a generalized version as well. Will fix.
> > + nor->flags & SNOR_F_SOFT_RESET)
> > + spi_nor_soft_reset(nor);
> > }
> > EXPORT_SYMBOL_GPL(spi_nor_restore);
> >
> > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> > index cd549042c53d..299685d15dc2 100644
> > --- a/include/linux/mtd/spi-nor.h
> > +++ b/include/linux/mtd/spi-nor.h
> > @@ -51,6 +51,8 @@
> > #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
> > #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
> > #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
> > +#define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
> > +#define SPINOR_OP_SRST 0x99 /* Software Reset */
> >
> > /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
> > #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
--
Regards,
Pratyush Yadav
next prev parent reply other threads:[~2020-07-20 16:11 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-23 18:30 [PATCH v10 00/17] mtd: spi-nor: add xSPI Octal DTR support Pratyush Yadav
2020-06-23 18:30 ` [PATCH v10 01/17] spi: spi-mem: allow specifying whether an op is DTR or not Pratyush Yadav
2020-07-08 16:22 ` Tudor.Ambarus
2020-07-13 3:55 ` Tudor.Ambarus
2020-06-23 18:30 ` [PATCH v10 02/17] spi: spi-mem: allow specifying a command's extension Pratyush Yadav
2020-07-13 6:15 ` Tudor.Ambarus
2020-06-23 18:30 ` [PATCH v10 03/17] spi: atmel-quadspi: reject DTR ops Pratyush Yadav
2020-07-13 6:19 ` Tudor.Ambarus
2020-06-23 18:30 ` [PATCH v10 04/17] spi: spi-mtk-nor: " Pratyush Yadav
2020-07-13 6:24 ` Tudor.Ambarus
2020-06-23 18:30 ` [PATCH v10 05/17] mtd: spi-nor: add support for DTR protocol Pratyush Yadav
2020-07-07 17:37 ` Tudor.Ambarus
2020-07-21 11:29 ` Pratyush Yadav
2020-09-29 15:42 ` Tudor.Ambarus
2020-09-29 16:29 ` Pratyush Yadav
2020-09-29 18:34 ` Tudor.Ambarus
2020-09-29 16:57 ` Vignesh Raghavendra
2020-06-23 18:30 ` [PATCH v10 06/17] mtd: spi-nor: sfdp: get command opcode extension type from BFPT Pratyush Yadav
2020-07-07 17:53 ` Tudor.Ambarus
2020-06-23 18:30 ` [PATCH v10 07/17] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table Pratyush Yadav
2020-07-08 16:01 ` Tudor.Ambarus
2020-07-20 16:38 ` Pratyush Yadav
2020-06-23 18:30 ` [PATCH v10 08/17] mtd: spi-nor: core: use dummy cycle and address width info from SFDP Pratyush Yadav
2020-07-08 16:03 ` Tudor.Ambarus
2020-07-20 16:24 ` Pratyush Yadav
2020-06-23 18:30 ` [PATCH v10 09/17] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode Pratyush Yadav
2020-06-23 18:30 ` [PATCH v10 10/17] mtd: spi-nor: core: enable octal DTR mode when possible Pratyush Yadav
2020-06-23 18:30 ` [PATCH v10 11/17] mtd: spi-nor: sfdp: do not make invalid quad enable fatal Pratyush Yadav
2020-07-13 9:33 ` Tudor.Ambarus
2020-06-23 18:30 ` [PATCH v10 12/17] mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT Pratyush Yadav
2020-07-08 16:08 ` Tudor.Ambarus
2020-07-20 16:21 ` Pratyush Yadav
2020-06-23 18:30 ` [PATCH v10 13/17] mtd: spi-nor: core: perform a Soft Reset on shutdown Pratyush Yadav
2020-07-08 16:10 ` Tudor.Ambarus
2020-07-20 16:11 ` Pratyush Yadav [this message]
2020-06-23 18:30 ` [PATCH v10 14/17] mtd: spi-nor: core: disable Octal DTR mode on suspend Pratyush Yadav
2020-06-23 18:30 ` [PATCH v10 15/17] mtd: spi-nor: core: expose spi_nor_default_setup() in core.h Pratyush Yadav
2020-06-23 18:30 ` [PATCH v10 16/17] mtd: spi-nor: spansion: add support for Cypress Semper flash Pratyush Yadav
2020-06-23 18:30 ` [PATCH v10 17/17] mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode Pratyush Yadav
2020-07-13 6:34 ` [PATCH v10 00/17] mtd: spi-nor: add xSPI Octal DTR support Tudor.Ambarus
2020-07-14 19:19 ` Mark Brown
2020-07-15 3:40 ` Tudor.Ambarus
2020-07-14 16:40 ` Mark Brown
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