From: Serge Semin <Sergey.Semin@baikalelectronics.ru> To: Mark Brown <broonie@kernel.org> Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>, Serge Semin <fancer.lancer@gmail.com>, Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>, Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>, Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>, Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>, Peter Ujfalusi <peter.ujfalusi@ti.com>, Andy Shevchenko <andy.shevchenko@gmail.com>, Andy Shevchenko <andriy.shevchenko@linux.intel.com>, Feng Tang <feng.tang@intel.com>, Vinod Koul <vkoul@kernel.org>, <linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH 2/8] spi: dw-dma: Fail DMA-based transfer if no Tx-buffer specified Date: Fri, 31 Jul 2020 10:59:47 +0300 Message-ID: <20200731075953.14416-3-Sergey.Semin@baikalelectronics.ru> (raw) In-Reply-To: <20200731075953.14416-1-Sergey.Semin@baikalelectronics.ru> Since commit 46164fde6b78 ("spi: dw: Fix Rx-only DMA transfers") if DMA interface is enabled, then Tx-buffer must be available in each SPI transfer. It's required since in order to activate the incoming data reception either DMA or CPU must be pushing data out to the SPI bus. But the DW APB SSI DMA driver code is still left in state as if Tx-buffer might be optional, which is no longer true. Let's fix it so an error would be returned if no Tx-buffer detected and DMA Tx would be always enabled. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- drivers/spi/spi-dw-dma.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c index 440679fa0764..ec721af61663 100644 --- a/drivers/spi/spi-dw-dma.c +++ b/drivers/spi/spi-dw-dma.c @@ -263,9 +263,6 @@ dw_spi_dma_prepare_tx(struct dw_spi *dws, struct spi_transfer *xfer) struct dma_slave_config txconf; struct dma_async_tx_descriptor *txdesc; - if (!xfer->tx_buf) - return NULL; - memset(&txconf, 0, sizeof(txconf)); txconf.direction = DMA_MEM_TO_DEV; txconf.dst_addr = dws->dma_addr; @@ -384,17 +381,19 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws, static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer) { - u16 imr = 0, dma_ctrl = 0; + u16 imr, dma_ctrl; - if (xfer->tx_buf) - dma_ctrl |= SPI_DMA_TDMAE; + if (!xfer->tx_buf) + return -EINVAL; + + /* Set the DMA handshaking interface */ + dma_ctrl = SPI_DMA_TDMAE; if (xfer->rx_buf) dma_ctrl |= SPI_DMA_RDMAE; dw_writel(dws, DW_SPI_DMACR, dma_ctrl); /* Set the interrupt mask */ - if (xfer->tx_buf) - imr |= SPI_INT_TXOI; + imr = SPI_INT_TXOI; if (xfer->rx_buf) imr |= SPI_INT_RXUI | SPI_INT_RXOI; spi_umask_intr(dws, imr); @@ -413,6 +412,8 @@ static int dw_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer) /* Prepare the TX dma transfer */ txdesc = dw_spi_dma_prepare_tx(dws, xfer); + if (!txdesc) + return -EINVAL; /* Prepare the RX dma transfer */ rxdesc = dw_spi_dma_prepare_rx(dws, xfer); @@ -424,17 +425,15 @@ static int dw_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer) dma_async_issue_pending(dws->rxchan); } - if (txdesc) { - set_bit(TX_BUSY, &dws->dma_chan_busy); - dmaengine_submit(txdesc); - dma_async_issue_pending(dws->txchan); - } + set_bit(TX_BUSY, &dws->dma_chan_busy); + dmaengine_submit(txdesc); + dma_async_issue_pending(dws->txchan); ret = dw_spi_dma_wait(dws, xfer); if (ret) return ret; - if (txdesc && dws->master->cur_msg->status == -EINPROGRESS) { + if (dws->master->cur_msg->status == -EINPROGRESS) { ret = dw_spi_dma_wait_tx_done(dws, xfer); if (ret) return ret; -- 2.27.0
next prev parent reply index Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-31 7:59 [PATCH 0/8] spi: dw-dma: Add max SG entries burst capability support Serge Semin 2020-07-31 7:59 ` [PATCH 1/8] spi: dw-dma: Set DMA Level registers on init Serge Semin 2020-07-31 7:59 ` Serge Semin [this message] 2020-07-31 7:59 ` [PATCH 3/8] spi: dw-dma: Configure the DMA channels in dma_setup Serge Semin 2020-07-31 9:16 ` Andy Shevchenko 2020-07-31 12:32 ` Serge Semin 2020-07-31 7:59 ` [PATCH 4/8] spi: dw-dma: Move DMA transfers submission to the channels prep methods Serge Semin 2020-07-31 9:15 ` Andy Shevchenko 2020-07-31 12:46 ` Serge Semin 2020-07-31 7:59 ` [PATCH 5/8] spi: dw-dma: Detach DMA transfer into a dedicated method Serge Semin 2020-07-31 7:59 ` [PATCH 6/8] spi: dw-dma: Move DMAC register cleanup to DMA transfer method Serge Semin 2020-07-31 7:59 ` [PATCH 7/8] spi: dw-dma: Pass exact data to the DMA submit and wait methods Serge Semin 2020-07-31 7:59 ` [PATCH 8/8] spi: dw-dma: Add one-by-one SG list entries transfer Serge Semin 2020-07-31 9:26 ` [PATCH 0/8] spi: dw-dma: Add max SG entries burst capability support Andy Shevchenko 2020-07-31 12:59 ` Serge Semin 2020-08-04 21:14 ` Mark Brown 2020-08-05 11:31 ` Vinod Koul
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