From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: Mark Brown <broonie@kernel.org>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>,
Serge Semin <fancer.lancer@gmail.com>,
Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>,
Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
Andy Shevchenko <andy.shevchenko@gmail.com>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Lars Povlsen <lars.povlsen@microchip.com>,
"wuxu . wu" <wuxu.wu@huawei.com>, Feng Tang <feng.tang@intel.com>,
Rob Herring <robh+dt@kernel.org>, <linux-spi@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 17/30] spi: dw: Refactor data IO procedure
Date: Sun, 20 Sep 2020 14:29:01 +0300 [thread overview]
Message-ID: <20200920112914.26501-18-Sergey.Semin@baikalelectronics.ru> (raw)
In-Reply-To: <20200920112914.26501-1-Sergey.Semin@baikalelectronics.ru>
The Tx and Rx data write/read procedure can be significantly simplified by
using Tx/Rx transfer lengths instead of the end pointers. By having the
Tx/Rx data leftover lengths (in the number of transfer words) we can get
rid of all subtraction and division operations utilized here and there in
the tx_max(), rx_max(), dw_writer() and dw_reader() methods. Such
modification will not only give us the more optimized IO procedures, but
will make the data IO methods much more readable than before.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
---
drivers/spi/spi-dw-core.c | 37 +++++++++++++++++--------------------
drivers/spi/spi-dw.h | 5 ++---
2 files changed, 19 insertions(+), 23 deletions(-)
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index 9102685c1523..84c1fdfd6e52 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -108,9 +108,8 @@ EXPORT_SYMBOL_GPL(dw_spi_set_cs);
/* Return the max entries we can fill into tx fifo */
static inline u32 tx_max(struct dw_spi *dws)
{
- u32 tx_left, tx_room, rxtx_gap;
+ u32 tx_room, rxtx_gap;
- tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
/*
@@ -121,18 +120,15 @@ static inline u32 tx_max(struct dw_spi *dws)
* shift registers. So a control from sw point of
* view is taken.
*/
- rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
- / dws->n_bytes;
+ rxtx_gap = dws->fifo_len - (dws->rx_len - dws->tx_len);
- return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
+ return min3((u32)dws->tx_len, tx_room, rxtx_gap);
}
/* Return the max entries we should read out of rx fifo */
static inline u32 rx_max(struct dw_spi *dws)
{
- u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
-
- return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
+ return min_t(u32, dws->rx_len, dw_readl(dws, DW_SPI_RXFLR));
}
static void dw_writer(struct dw_spi *dws)
@@ -141,15 +137,16 @@ static void dw_writer(struct dw_spi *dws)
u16 txw = 0;
while (max--) {
- /* Set the tx word if the transfer's original "tx" is not null */
- if (dws->tx_end - dws->len) {
+ if (dws->tx) {
if (dws->n_bytes == 1)
txw = *(u8 *)(dws->tx);
else
txw = *(u16 *)(dws->tx);
+
+ dws->tx += dws->n_bytes;
}
dw_write_io_reg(dws, DW_SPI_DR, txw);
- dws->tx += dws->n_bytes;
+ --dws->tx_len;
}
}
@@ -160,14 +157,15 @@ static void dw_reader(struct dw_spi *dws)
while (max--) {
rxw = dw_read_io_reg(dws, DW_SPI_DR);
- /* Care rx only if the transfer's original "rx" is not null */
- if (dws->rx_end - dws->len) {
+ if (dws->rx) {
if (dws->n_bytes == 1)
*(u8 *)(dws->rx) = rxw;
else
*(u16 *)(dws->rx) = rxw;
+
+ dws->rx += dws->n_bytes;
}
- dws->rx += dws->n_bytes;
+ --dws->rx_len;
}
}
@@ -192,7 +190,7 @@ static irqreturn_t interrupt_transfer(struct dw_spi *dws)
}
dw_reader(dws);
- if (dws->rx_end == dws->rx) {
+ if (!dws->rx_len) {
spi_mask_intr(dws, 0xff);
spi_finalize_current_transfer(dws->master);
return IRQ_HANDLED;
@@ -299,12 +297,11 @@ static int dw_spi_transfer_one(struct spi_controller *master,
dws->dma_mapped = 0;
dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
dws->tx = (void *)transfer->tx_buf;
- dws->tx_end = dws->tx + transfer->len;
+ dws->tx_len = transfer->len / dws->n_bytes;
dws->rx = transfer->rx_buf;
- dws->rx_end = dws->rx + transfer->len;
- dws->len = transfer->len;
+ dws->rx_len = dws->tx_len;
- /* Ensure dw->rx and dw->rx_end are visible */
+ /* Ensure the data above is visible for all CPUs */
smp_mb();
spi_enable_chip(dws, 0);
@@ -331,7 +328,7 @@ static int dw_spi_transfer_one(struct spi_controller *master,
return ret;
}
} else {
- txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
+ txlevel = min_t(u16, dws->fifo_len / 2, dws->tx_len);
dw_writel(dws, DW_SPI_TXFTLR, txlevel);
/* Set the interrupt mask */
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 2a2346438564..cfc9f63acde4 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -147,11 +147,10 @@ struct dw_spi {
void (*set_cs)(struct spi_device *spi, bool enable);
/* Current message transfer state info */
- size_t len;
void *tx;
- void *tx_end;
+ unsigned int tx_len;
void *rx;
- void *rx_end;
+ unsigned int rx_len;
int dma_mapped;
u8 n_bytes; /* current is a 1/2 bytes op */
irqreturn_t (*transfer_handler)(struct dw_spi *dws);
--
2.27.0
next prev parent reply other threads:[~2020-09-20 11:31 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-20 11:28 [PATCH 00/30] spi: dw: Add full Baikal-T1 SPI Controllers support Serge Semin
2020-09-20 11:28 ` [PATCH 01/30] spi: dw: Discard IRQ threshold macro Serge Semin
2020-09-20 11:28 ` [PATCH 02/30] spi: dw: Use ternary op to init set_cs callback Serge Semin
2020-09-29 13:11 ` Mark Brown
2020-09-29 21:55 ` Serge Semin
2020-09-30 14:57 ` Serge Semin
2020-09-30 15:01 ` Mark Brown
2020-09-30 15:07 ` Serge Semin
2020-09-20 11:28 ` [PATCH 03/30] spi: dw: Initialize n_bytes before the memory barrier Serge Semin
2020-09-29 13:12 ` Mark Brown
2020-09-29 22:05 ` Serge Semin
2020-09-20 11:28 ` [PATCH 04/30] Revert: spi: spi-dw: Add lock protect dw_spi rx/tx to prevent concurrent calls Serge Semin
2020-09-29 13:28 ` Mark Brown
2020-09-29 22:08 ` Serge Semin
2020-09-20 11:28 ` [PATCH 05/30] spi: dw: Clear IRQ status on DW SPI controller reset Serge Semin
2020-09-20 11:28 ` [PATCH 06/30] spi: dw: Disable all IRQs when controller is unused Serge Semin
2020-09-20 11:28 ` [PATCH 07/30] spi: dw: Use relaxed IO-methods to access FIFOs Serge Semin
2020-09-20 11:28 ` [PATCH 08/30] spi: dw: Discard DW SSI chip type storages Serge Semin
2020-09-20 11:28 ` [PATCH 09/30] spi: dw: Convert CS-override to DW SPI capabilities Serge Semin
2020-09-20 11:28 ` [PATCH 10/30] spi: dw: Add KeemBay Master capability Serge Semin
2020-09-20 11:28 ` [PATCH 11/30] spi: dw: Add DWC SSI capability Serge Semin
2020-09-29 13:52 ` Mark Brown
2020-09-29 22:17 ` Serge Semin
2020-09-30 15:03 ` Serge Semin
2020-09-30 15:41 ` Mark Brown
2020-09-30 15:53 ` Serge Semin
2020-09-20 11:28 ` [PATCH 12/30] spi: dw: Detach SPI device specific CR0 config method Serge Semin
2020-09-20 11:28 ` [PATCH 13/30] spi: dw: Update SPI bus speed in a config function Serge Semin
2020-09-20 11:28 ` [PATCH 14/30] spi: dw: Simplify the SPI bus speed config procedure Serge Semin
2020-09-20 11:28 ` [PATCH 15/30] spi: dw: Update Rx sample delay in the config function Serge Semin
2020-09-20 11:29 ` [PATCH 16/30] spi: dw: Add DW SPI controller config structure Serge Semin
2020-09-20 11:29 ` Serge Semin [this message]
2020-09-20 11:29 ` [PATCH 18/30] spi: dw: Refactor IRQ-based SPI transfer procedure Serge Semin
2020-09-20 11:29 ` [PATCH 19/30] spi: dw: Perform IRQ setup in a dedicated function Serge Semin
2020-09-20 11:29 ` [PATCH 20/30] spi: dw: Unmask IRQs after enabling the chip Serge Semin
2020-09-20 11:29 ` [PATCH 21/30] spi: dw: Discard chip enabling on DMA setup error Serge Semin
2020-09-20 11:29 ` [PATCH 22/30] spi: dw: De-assert chip-select on reset Serge Semin
2020-09-20 11:29 ` [PATCH 23/30] spi: dw: Explicitly de-assert CS on SPI transfer completion Serge Semin
2020-09-20 11:29 ` [PATCH 24/30] spi: dw: Move num-of retries parameter to the header file Serge Semin
2020-09-20 11:29 ` [PATCH 25/30] spi: dw: Add generic DW SSI status-check method Serge Semin
2020-09-20 11:29 ` [PATCH 26/30] spi: dw: Add memory operations support Serge Semin
2020-09-20 11:29 ` [PATCH 27/30] spi: dw: Introduce max mem-ops SPI bus frequency setting Serge Semin
2020-09-20 11:29 ` [PATCH 28/30] spi: dw: Add poll-based SPI transfers support Serge Semin
2020-09-20 11:29 ` [PATCH 29/30] dt-bindings: spi: dw: Add Baikal-T1 SPI Controllers Serge Semin
2020-09-29 16:58 ` Rob Herring
2020-09-20 11:41 ` [PATCH 30/30] spi: dw: Add Baikal-T1 SPI Controller glue driver Serge Semin
2020-09-29 14:43 ` [PATCH 00/30] spi: dw: Add full Baikal-T1 SPI Controllers support Mark Brown
2020-09-29 22:43 ` Serge Semin
2020-09-30 11:04 ` Mark Brown
2020-09-30 13:11 ` Serge Semin
2020-09-30 14:43 ` Mark Brown
2020-09-29 16:23 ` Mark Brown
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