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Thu, 1 Oct 2020 15:22:48 +0000 (GMT) From: =?UTF-8?q?=C5=81ukasz=20Stelmach?= To: Kukjin Kim , Krzysztof Kozlowski , Tomasz Figa , Andi Shyti , Mark Brown , linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: m.szyprowski@samsung.com, b.zolnierkie@samsung.com, =?UTF-8?q?=C5=81ukasz=20Stelmach?= Subject: [PATCH v2 RESEND 7/9] spi: spi-s3c64xx: Ensure cur_speed holds actual clock value Date: Thu, 1 Oct 2020 17:21:46 +0200 Message-Id: <20201001152148.29747-8-l.stelmach@samsung.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001152148.29747-1-l.stelmach@samsung.com> MIME-Version: 1.0 Organization: Samsung R&D Institute Poland Content-Transfer-Encoding: 8bit X-Brightmail-Tracker: H4sIAAAAAAAAA02Se0hTYRjG+Xa2c47i9DgXvthFHAUpOBMrDqmRZjH/6kYYZdnMg5PclB1n aoFmqGWmqVi2pKQsRcrLvF8QndFK04FBaqk51LwheSUVyzweI/973u/9vc/7vPCRmKRG5ERG aGIYrUYZKcOthbXvV8zugYu6kAOPDAT9cnlcQFfml4voPMsoTmeNTGO02VxB0P3GEkQbRr6I 6M+NBTidb24R0Lfn+gn67btBgi5tXEPHbBS9RfOYokE/SCgMpfdwRVVRoiKzuhQpFgx7TuMX rX3CmMiIWEbrcfSqtcpkfo2i1/G4pcY0LAlNidIRQQJ1EFZ2pCMrUkKVIBjqck9H1ht6EUHm r2IRXywgmLVMCziK47M7LEK+UYygKm+V4ItxBM3LA4ijcMoPsl592ByXUnUCyF4wC7kGRukg o8GIpyOSdKCCYeJrHCeF1D6YWAngCDHlDWtLzwl+mTOkFdfhnLaifKA7ux3nGXv4+GR009GO coM3yb1b7s5wp+Ypxs8OEdDUFM7rACj7PoN47QBTpuot/13QmZsh5CIAlQi5OYe5xEBlIKgt WBbyjDcMdK9uJsYoVyhv9OBxP5g1+/LSFvpm7PkAtpBT+xjjn8VwN1XCe+yFsqzmLT8neDBV gh4imX7bKfpt8fX/VxUirBQ5MjpWHc6wnhrmhpxVqlmdJlx+LUptQBufqfOPab4eLfWEGhFF IpmNWGXUhUhEylg2Xm1EQGIyqdi/q/OKRBymjE9gtFEhWl0kwxrRTlIocxR7vZi8LKHClTHM dYaJZrT/ugLSyikJadpCbLx6mLDfXir5D4XUBSusN4amoAR3//vrFrvowSA3+Ug3Cp4Y6xo9 YXPmXIdD6thx/eScy5Fo07ihMnB//6eZ5OHqPt+zPysO+Reww+1BzxLOn6o0JY8SytVbQ99a UopbXOnW1uALc2fN0oXdResNze156ptyy8mZS1FtRTIhq1J6umFaVvkX8CCHJEgDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrNIsWRmVeSWpSXmKPExsVy+t/xu7oeX0rjDf5161ss/vGcyWLjjPWs FlMfPmGz6H/8mtni/PkN7BY3D61gtNj0+BqrxeVdc9gsZpzfx2TR+PEmu8XaI3fZLVbt+sPo wONxfcknZo+ds+6ye2xa1cnmsXlJvUffllWMHp83yQWwRenZFOWXlqQqZOQXl9gqRRtaGOkZ WlroGZlY6hkam8daGZkq6dvZpKTmZJalFunbJehlHD+/jLHgP1vF113tzA2Mr1i7GDk5JARM JCaeesjSxcjFISSwlFFi96r7QA4HUEJKYuXcdIgaYYk/17rYIGqeMkrc7pzGDJJgE3CU6F96 ghUkISKwn0ni0gWQZk4OZoFyiUuznrOD2MICURKPV+xgBxnKIqAq8eKnC0iYV8Ba4s/X+ewQ C+Ql2pdvZwOxOQVsJM5NPAxmCwnkSuzefZQNol5Q4uTMJ2C3MQuoS6yfJwQS5hfQkljTdB1q q7xE89bZzBMYhWYh6ZiF0DELSdUCRuZVjCKppcW56bnFhnrFibnFpXnpesn5uZsYgRG57djP zTsYL20MPsQowMGoxMMrcKA0Xog1say4MvcQowQHs5IIr9PZ03FCvCmJlVWpRfnxRaU5qcWH GE2BvpzILCWanA9MFnkl8YamhuYWlobmxubGZhZK4rwdAgdjhATSE0tSs1NTC1KLYPqYODil GhgTtsZsE2/60f6nz/z6+mmBz2qvVWn/vvY1Szt3aYPI4vwgp5IlHM8TNi1dMe3oi6hc2zN7 JV+3Tv0vmBQ479LD+v/Fzm7hVUvWrmI9PG8xf7J3+zFZeUuNeTnLWVeovTrU6KARVsYpPP3H xj82v8/Me+r7K2H147lanNt2V2+c9z99RUwBN5evEktxRqKhFnNRcSIAweqE8t4CAAA= X-CMS-MailID: 20201001152248eucas1p132a63f588f62d902879322ebadd67173 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20201001152248eucas1p132a63f588f62d902879322ebadd67173 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201001152248eucas1p132a63f588f62d902879322ebadd67173 References: <20200821161401.11307-1-l.stelmach@samsung.com> <20201001152148.29747-1-l.stelmach@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Make sure the cur_speed value used in s3c64xx_enable_datapath() to configure DMA channel and in s3c64xx_wait_for_*() to calculate the transfer timeout is set to the actual value of (half) the clock speed. Suggested-by: Tomasz Figa Signed-off-by: Łukasz Stelmach --- drivers/spi/spi-s3c64xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 02de734b8ab1..89c162efe355 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -626,6 +626,7 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); if (ret) return ret; + sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2; } else { /* Configure Clock */ val = readl(regs + S3C64XX_SPI_CLK_CFG); -- 2.26.2