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* [PATCH v1 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC
@ 2020-10-16  9:31 Ramuthevar,Vadivel MuruganX
  2020-10-16  9:31 ` [PATCH v1 1/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Ramuthevar,Vadivel MuruganX
                   ` (5 more replies)
  0 siblings, 6 replies; 13+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-10-16  9:31 UTC (permalink / raw)
  To: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi, robh+dt
  Cc: devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
	richard, cheol.yong.kim, qi-ming.wu, Ramuthevar,Vadivel MuruganX

Add QSPI controller support for Intel LGM SoC.

Note from Vignesh(mtd subsystem maintainer):
This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add
support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX
<vadivel.muruganx.ramuthevar@linux.intel.com> that intended to move
cadence-quadspi driver to spi-mem framework

Those patches were trying to accomplish too many things in a single set
of patches and need to split into smaller patches. This is reduced
version of above series.

Changes that are intended to make migration easy are split into separate
patches. Patches 1 to 3 drop features that cannot be supported under
spi-mem at the moment (backward compatibility is maintained).
Patch 4-5 are trivial cleanups. Patch 6 does the actual conversion to
spi-mem and patch 7 moves the driver to drivers/spi folder.

I have tested both INDAC mode (used by non TI platforms like Altera
SoCFPGA) and DAC mode (used by TI platforms) on TI EVMs.

Patches to move move bindings over to
"Documentation/devicetree/bindings/spi/" directory and also conversion
of bindig doc to YAML will be posted separately.  Support for Intel
platform would follow that.

Reference:
	https://lkml.org/lkml/2020/6/1/50

Ramuthevar Vadivel Murugan (6):
  spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi
  dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml
  dt-bindings: spi: Add compatible for Intel LGM SoC
  spi: cadence-quadspi: Add QSPI support for Intel LGM SoC
  spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
  spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC

 .../devicetree/bindings/mtd/cadence-quadspi.txt    |  67 ---------
 .../devicetree/bindings/spi/cadence-quadspi.yaml   | 149 +++++++++++++++++++++
 drivers/spi/Kconfig                                |   2 +-
 drivers/spi/spi-cadence-quadspi.c                  |  29 ++++
 4 files changed, 179 insertions(+), 68 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
 create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml

-- 
2.11.0


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v1 1/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi
  2020-10-16  9:31 [PATCH v1 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
@ 2020-10-16  9:31 ` Ramuthevar,Vadivel MuruganX
  2020-10-19 21:26   ` Rob Herring
  2020-10-16  9:31 ` [PATCH v1 2/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Ramuthevar,Vadivel MuruganX
                   ` (4 subsequent siblings)
  5 siblings, 1 reply; 13+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-10-16  9:31 UTC (permalink / raw)
  To: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi, robh+dt
  Cc: devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
	richard, cheol.yong.kim, qi-ming.wu, Ramuthevar Vadivel Murugan

From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>

Move the Documentation/devicetree/bindings/mtd/cadence-quadspi.txt to
Documentation/devicetree/bindings/spi/

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
 Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt (100%)

diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
similarity index 100%
rename from Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
rename to Documentation/devicetree/bindings/spi/cadence-quadspi.txt
-- 
2.11.0


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v1 2/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml
  2020-10-16  9:31 [PATCH v1 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
  2020-10-16  9:31 ` [PATCH v1 1/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Ramuthevar,Vadivel MuruganX
@ 2020-10-16  9:31 ` Ramuthevar,Vadivel MuruganX
  2020-10-16 16:18   ` Mark Brown
  2020-10-19 21:35   ` Rob Herring
  2020-10-16  9:31 ` [PATCH v1 3/6] dt-bindings: spi: Add compatible for Intel LGM SoC Ramuthevar,Vadivel MuruganX
                   ` (3 subsequent siblings)
  5 siblings, 2 replies; 13+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-10-16  9:31 UTC (permalink / raw)
  To: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi, robh+dt
  Cc: devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
	richard, cheol.yong.kim, qi-ming.wu, Ramuthevar Vadivel Murugan

From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>

Convert the cadence-quadspi.txt documentation to cadence-quadspi.yaml
remove the cadence-quadspi.txt from Documentation/devicetree/bindings/spi/

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
 .../devicetree/bindings/spi/cadence-quadspi.txt    |  67 ----------
 .../devicetree/bindings/spi/cadence-quadspi.yaml   | 148 +++++++++++++++++++++
 2 files changed, 148 insertions(+), 67 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt
 create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml

diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
deleted file mode 100644
index 945be7d5b236..000000000000
--- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-* Cadence Quad SPI controller
-
-Required properties:
-- compatible : should be one of the following:
-	Generic default - "cdns,qspi-nor".
-	For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
-	For TI AM654 SoC  - "ti,am654-ospi", "cdns,qspi-nor".
-- reg : Contains two entries, each of which is a tuple consisting of a
-	physical address and length. The first entry is the address and
-	length of the controller register set. The second entry is the
-	address and length of the QSPI Controller data area.
-- interrupts : Unit interrupt specifier for the controller interrupt.
-- clocks : phandle to the Quad SPI clock.
-- cdns,fifo-depth : Size of the data FIFO in words.
-- cdns,fifo-width : Bus width of the data FIFO in bytes.
-- cdns,trigger-address : 32-bit indirect AHB trigger address.
-
-Optional properties:
-- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
-- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
-  the read data rather than the QSPI clock. Make sure that QSPI return
-  clock is populated on the board before using this property.
-
-Optional subnodes:
-Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
-custom properties:
-- cdns,read-delay : Delay for read capture logic, in clock cycles
-- cdns,tshsl-ns : Delay in nanoseconds for the length that the master
-                  mode chip select outputs are de-asserted between
-		  transactions.
-- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being
-                  de-activated and the activation of another.
-- cdns,tchsh-ns : Delay in nanoseconds between last bit of current
-                  transaction and deasserting the device chip select
-		  (qspi_n_ss_out).
-- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
-                  and first bit transfer.
-- resets	: Must contain an entry for each entry in reset-names.
-		  See ../reset/reset.txt for details.
-- reset-names	: Must include either "qspi" and/or "qspi-ocp".
-
-Example:
-
-	qspi: spi@ff705000 {
-		compatible = "cdns,qspi-nor";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0xff705000 0x1000>,
-		      <0xffa00000 0x1000>;
-		interrupts = <0 151 4>;
-		clocks = <&qspi_clk>;
-		cdns,is-decoded-cs;
-		cdns,fifo-depth = <128>;
-		cdns,fifo-width = <4>;
-		cdns,trigger-address = <0x00000000>;
-		resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
-		reset-names = "qspi", "qspi-ocp";
-
-		flash0: n25q00@0 {
-			...
-			cdns,read-delay = <4>;
-			cdns,tshsl-ns = <50>;
-			cdns,tsd2d-ns = <50>;
-			cdns,tchsh-ns = <4>;
-			cdns,tslch-ns = <4>;
-		};
-	};
diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
new file mode 100644
index 000000000000..6ed8122a1326
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/cadence-quadspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence Quad SPI controller
+
+maintainers:
+  - Vadivel Murugan <vadivel.muruganx.ramuthevar@intel.com>
+
+allOf:
+  - $ref: "spi-controller.yaml#"
+
+properties:
+  compatible:
+    items:
+      - const: cdns,qspi-nor
+      - const: ti,k2g-qspi, cdns,qspi-nor
+      - const: ti,am654-ospi, cdns,qspi-nor
+
+    description:
+      Should be one of the above supported compatible strings.
+      optional properties
+      "cdns,is-decoded-cs" - Flag to indicate whether decoder is used or not.
+      "cdns,rclk-en" - Flag to indicate that QSPI return clock is used to latch
+      the read data rather than the QSPI clock. Make sure that QSPI return
+      clock is populated on the board before using this property.
+
+  reg:
+    maxItems: 2
+
+    description:
+      Contains two entries, each of which is a tuple consisting of a
+      physical address and length. The first entry is the address and
+      length of the controller register set. The second entry is the
+      address and length of the QSPI Controller data area.
+
+  interrupts:
+    maxItems: 1
+    description:
+      Unit interrupt specifier for the controller interrupt.
+
+  clocks:
+    maxItems: 1
+    description:
+      phandle to the Quad SPI clock.
+
+  cdns,fifo-depth:
+    description:
+      Size of the data FIFO in words.
+    allOf:
+      - $ref: "/schemas/types.yaml#/definitions/uint32"
+      - enum: [ 128, 256 ]
+      - default: 128
+
+  cdns,fifo-width:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Bus width of the data FIFO in bytes.
+    multipleOf: 4
+
+  cdns,trigger-address:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      32-bit indirect AHB trigger address.
+
+  resets:
+     description:
+       Must contain an entry for each entry in reset-names.
+       See ../reset/reset.txt for details.
+
+  reset-names:
+    description:
+      Must include either "qspi" and/or "qspi-ocp".
+
+# subnode's properties
+patternProperties:
+  "@[0-9a-f]+$":
+    type: object
+    description:
+      flash device uses the subnodes below defined properties.
+
+  cdns,read-delay:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Delay for read capture logic, in clock cycles.
+
+  cdns,tshsl-ns:
+    description: |
+      Delay in nanoseconds for the length that the master mode chip select
+      outputs are de-asserted between transactions.
+
+  cdns,tsd2d-ns:
+    description: |
+      Delay in nanoseconds between one chip select being de-activated
+      and the activation of another.
+
+  cdns,tchsh-ns:
+    description: |
+      Delay in nanoseconds between last bit of current transaction and
+      deasserting the device chip select (qspi_n_ss_out).
+
+  cdns,tslch-ns:
+    description: |
+      Delay in nanoseconds between setting qspi_n_ss_out low and
+      first bit transfer.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - cdns,fifo-depth
+  - cdns,fifo-width
+  - cdns,trigger-address
+  - resets
+  - reset-names
+
+examples:
+  - |
+    qspi: spi@ff705000 {
+      compatible = "cadence,qspi";
+      #address-cells = <1>;
+      #size-cells = <0>;
+      reg = <0xff705000 0x1000>,
+            <0xffa00000 0x1000>;
+      interrupts = <0 151 4>;
+      clocks = <&qspi_clk>;
+      cdns,fifo-depth = <128>;
+      cdns,fifo-width = <4>;
+      cdns,trigger-address = <0x00000000>;
+      resets = <&rst 0x1>, <&rst 0x2>;
+      reset-names = "qspi", "qspi-ocp";
+
+      flash@0 {
+              compatible = "jedec,spi-nor";
+              reg = <0x0>;
+              cdns,read-delay = <4>;
+              cdns,tshsl-ns = <50>;
+              cdns,tsd2d-ns = <50>;
+              cdns,tchsh-ns = <4>;
+              cdns,tslch-ns = <4>;
+     };
+
+    };
+
+...
-- 
2.11.0


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v1 3/6] dt-bindings: spi: Add compatible for Intel LGM SoC
  2020-10-16  9:31 [PATCH v1 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
  2020-10-16  9:31 ` [PATCH v1 1/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Ramuthevar,Vadivel MuruganX
  2020-10-16  9:31 ` [PATCH v1 2/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Ramuthevar,Vadivel MuruganX
@ 2020-10-16  9:31 ` Ramuthevar,Vadivel MuruganX
  2020-10-16  9:31 ` [PATCH v1 4/6] spi: cadence-quadspi: Add QSPI support " Ramuthevar,Vadivel MuruganX
                   ` (2 subsequent siblings)
  5 siblings, 0 replies; 13+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-10-16  9:31 UTC (permalink / raw)
  To: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi, robh+dt
  Cc: devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
	richard, cheol.yong.kim, qi-ming.wu, Ramuthevar Vadivel Murugan

From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>

Add compatible string for Intel LGM SoC.

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
index 6ed8122a1326..8b1e01159d2d 100644
--- a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
+++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
@@ -18,6 +18,7 @@ properties:
       - const: cdns,qspi-nor
       - const: ti,k2g-qspi, cdns,qspi-nor
       - const: ti,am654-ospi, cdns,qspi-nor
+      - const: intel,lgm-qspi, cdns,qspi-nor
 
     description:
       Should be one of the above supported compatible strings.
-- 
2.11.0


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v1 4/6] spi: cadence-quadspi: Add QSPI support for Intel LGM SoC
  2020-10-16  9:31 [PATCH v1 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
                   ` (2 preceding siblings ...)
  2020-10-16  9:31 ` [PATCH v1 3/6] dt-bindings: spi: Add compatible for Intel LGM SoC Ramuthevar,Vadivel MuruganX
@ 2020-10-16  9:31 ` Ramuthevar,Vadivel MuruganX
  2020-10-16 16:33   ` Mark Brown
  2020-10-16  9:31 ` [PATCH v1 5/6] spi: cadence-quadspi: Disable the DAC " Ramuthevar,Vadivel MuruganX
  2020-10-16  9:31 ` [PATCH v1 6/6] spi: cadence-quadspi: Add multi-chipselect support " Ramuthevar,Vadivel MuruganX
  5 siblings, 1 reply; 13+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-10-16  9:31 UTC (permalink / raw)
  To: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi, robh+dt
  Cc: devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
	richard, cheol.yong.kim, qi-ming.wu, Ramuthevar Vadivel Murugan

From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>

Add QSPI controller support for Intel LGM SoC.

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
 drivers/spi/Kconfig               | 2 +-
 drivers/spi/spi-cadence-quadspi.c | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index d2c976e55b8b..926da61eee5a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -203,7 +203,7 @@ config SPI_CADENCE
 
 config SPI_CADENCE_QUADSPI
 	tristate "Cadence Quad SPI controller"
-	depends on OF && (ARM || ARM64 || COMPILE_TEST)
+	depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST)
 	help
 	  Enable support for the Cadence Quad SPI Flash controller.
 
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 40938cf3806d..d7b10c46fa70 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1401,6 +1401,9 @@ static const struct of_device_id cqspi_dt_ids[] = {
 		.compatible = "ti,am654-ospi",
 		.data = &am654_ospi,
 	},
+	{
+		.compatible = "intel,lgm-qspi",
+	},
 	{ /* end of table */ }
 };
 
-- 
2.11.0


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v1 5/6] spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
  2020-10-16  9:31 [PATCH v1 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
                   ` (3 preceding siblings ...)
  2020-10-16  9:31 ` [PATCH v1 4/6] spi: cadence-quadspi: Add QSPI support " Ramuthevar,Vadivel MuruganX
@ 2020-10-16  9:31 ` Ramuthevar,Vadivel MuruganX
  2020-10-16  9:31 ` [PATCH v1 6/6] spi: cadence-quadspi: Add multi-chipselect support " Ramuthevar,Vadivel MuruganX
  5 siblings, 0 replies; 13+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-10-16  9:31 UTC (permalink / raw)
  To: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi, robh+dt
  Cc: devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
	richard, cheol.yong.kim, qi-ming.wu, Ramuthevar Vadivel Murugan

From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>

On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
Direct Access Controller(DAC).

This patch adds a quirk to disable the Direct Access Controller
for data transfer instead it uses indirect data transfer.

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
 drivers/spi/spi-cadence-quadspi.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index d7b10c46fa70..3d017b484114 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1106,6 +1106,13 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
 	reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
 	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 
+	/* Disable direct access controller */
+	if (!cqspi->use_direct_mode) {
+		reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
+		reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
+		writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+	}
+
 	cqspi_controller_enable(cqspi, 1);
 }
 
@@ -1388,6 +1395,10 @@ static const struct cqspi_driver_platdata am654_ospi = {
 	.quirks = CQSPI_NEEDS_WR_DELAY,
 };
 
+static const struct cqspi_driver_platdata intel_lgm_qspi = {
+	.quirks = CQSPI_DISABLE_DAC_MODE,
+};
+
 static const struct of_device_id cqspi_dt_ids[] = {
 	{
 		.compatible = "cdns,qspi-nor",
@@ -1403,6 +1414,7 @@ static const struct of_device_id cqspi_dt_ids[] = {
 	},
 	{
 		.compatible = "intel,lgm-qspi",
+		.data = &intel_lgm_qspi,
 	},
 	{ /* end of table */ }
 };
-- 
2.11.0


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v1 6/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
  2020-10-16  9:31 [PATCH v1 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
                   ` (4 preceding siblings ...)
  2020-10-16  9:31 ` [PATCH v1 5/6] spi: cadence-quadspi: Disable the DAC " Ramuthevar,Vadivel MuruganX
@ 2020-10-16  9:31 ` Ramuthevar,Vadivel MuruganX
  5 siblings, 0 replies; 13+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-10-16  9:31 UTC (permalink / raw)
  To: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi, robh+dt
  Cc: devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
	richard, cheol.yong.kim, qi-ming.wu, Ramuthevar Vadivel Murugan

From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>

Add multiple chipselect support for Intel LGM SoCs,
currently QSPI-NOR and QSPI-NAND supported.

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
 drivers/spi/spi-cadence-quadspi.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 3d017b484114..3bf6d3697631 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -38,6 +38,7 @@
 
 /* Capabilities */
 #define CQSPI_SUPPORTS_OCTAL		BIT(0)
+#define CQSPI_SUPPORTS_MULTI_CHIPSELECT BIT(1)
 
 struct cqspi_st;
 
@@ -75,6 +76,7 @@ struct cqspi_st {
 	bool			is_decoded_cs;
 	u32			fifo_depth;
 	u32			fifo_width;
+	u32			num_chipselect;
 	bool			rclk_en;
 	u32			trigger_address;
 	u32			wr_delay;
@@ -1070,6 +1072,14 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
 		return -ENXIO;
 	}
 
+	if (!cqspi->use_direct_mode) {
+		if (of_property_read_u32(np, "num-chipselect",
+					 &cqspi->num_chipselect)) {
+			dev_err(dev, "couldn't determine number of cs\n");
+			return -ENXIO;
+		}
+	}
+
 	cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
 
 	return 0;
@@ -1307,6 +1317,9 @@ static int cqspi_probe(struct platform_device *pdev)
 	cqspi->current_cs = -1;
 	cqspi->sclk = 0;
 
+	if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT)
+		master->num_chipselect = cqspi->num_chipselect;
+
 	ret = cqspi_setup_flash(cqspi);
 	if (ret) {
 		dev_err(dev, "failed to setup flash parameters %d\n", ret);
@@ -1396,6 +1409,7 @@ static const struct cqspi_driver_platdata am654_ospi = {
 };
 
 static const struct cqspi_driver_platdata intel_lgm_qspi = {
+	.hwcaps_mask = CQSPI_SUPPORTS_MULTI_CHIPSELECT,
 	.quirks = CQSPI_DISABLE_DAC_MODE,
 };
 
-- 
2.11.0


^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v1 2/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml
  2020-10-16  9:31 ` [PATCH v1 2/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Ramuthevar,Vadivel MuruganX
@ 2020-10-16 16:18   ` Mark Brown
  2020-10-19  6:22     ` Ramuthevar, Vadivel MuruganX
  2020-10-19 21:35   ` Rob Herring
  1 sibling, 1 reply; 13+ messages in thread
From: Mark Brown @ 2020-10-16 16:18 UTC (permalink / raw)
  To: Ramuthevar,Vadivel MuruganX
  Cc: vigneshr, tudor.ambarus, linux-kernel, linux-spi, robh+dt,
	devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
	richard, cheol.yong.kim, qi-ming.wu


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On Fri, Oct 16, 2020 at 05:31:34PM +0800, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> 
> Convert the cadence-quadspi.txt documentation to cadence-quadspi.yaml
> remove the cadence-quadspi.txt from Documentation/devicetree/bindings/spi/

Please make YAML conversions the last thing in any patch series -
there's sometimes a backlog on reviews as the DT maintainers are very
busy so this means that delays with them don't hold the rest of the
series up.

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^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v1 4/6] spi: cadence-quadspi: Add QSPI support for Intel LGM SoC
  2020-10-16  9:31 ` [PATCH v1 4/6] spi: cadence-quadspi: Add QSPI support " Ramuthevar,Vadivel MuruganX
@ 2020-10-16 16:33   ` Mark Brown
  2020-10-19  6:26     ` Ramuthevar, Vadivel MuruganX
  0 siblings, 1 reply; 13+ messages in thread
From: Mark Brown @ 2020-10-16 16:33 UTC (permalink / raw)
  To: Ramuthevar,Vadivel MuruganX
  Cc: vigneshr, tudor.ambarus, linux-kernel, linux-spi, robh+dt,
	devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
	richard, cheol.yong.kim, qi-ming.wu


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On Fri, Oct 16, 2020 at 05:31:36PM +0800, Ramuthevar,Vadivel MuruganX wrote:

> +	depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST)

> +	{
> +		.compatible = "intel,lgm-qspi",
> +	},

This is an x86 SoC (or SoC series) - is it really going to use DT for
the firmware interfaces?  It's not specifically a problem, just
surprising to see something other than ACPI.  Or is the intention to use
PRP0001?  There's a new comaptible here which wasn't really the use case
for PRP0001.  Like I say not really a problem, just curious.

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^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v1 2/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml
  2020-10-16 16:18   ` Mark Brown
@ 2020-10-19  6:22     ` Ramuthevar, Vadivel MuruganX
  0 siblings, 0 replies; 13+ messages in thread
From: Ramuthevar, Vadivel MuruganX @ 2020-10-19  6:22 UTC (permalink / raw)
  To: Mark Brown
  Cc: vigneshr, tudor.ambarus, linux-kernel, linux-spi, robh+dt,
	devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
	richard, cheol.yong.kim, qi-ming.wu

Hi Mark,

On 17/10/2020 12:18 am, Mark Brown wrote:
> On Fri, Oct 16, 2020 at 05:31:34PM +0800, Ramuthevar,Vadivel MuruganX wrote:
>> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>>
>> Convert the cadence-quadspi.txt documentation to cadence-quadspi.yaml
>> remove the cadence-quadspi.txt from Documentation/devicetree/bindings/spi/
> 
> Please make YAML conversions the last thing in any patch series -
> there's sometimes a backlog on reviews as the DT maintainers are very
> busy so this means that delays with them don't hold the rest of the
> series up.
Thank you for the comment and suggestions...
Sure, will do that accordingly.

Regards
Vadivel
> 

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v1 4/6] spi: cadence-quadspi: Add QSPI support for Intel LGM SoC
  2020-10-16 16:33   ` Mark Brown
@ 2020-10-19  6:26     ` Ramuthevar, Vadivel MuruganX
  0 siblings, 0 replies; 13+ messages in thread
From: Ramuthevar, Vadivel MuruganX @ 2020-10-19  6:26 UTC (permalink / raw)
  To: Mark Brown
  Cc: vigneshr, tudor.ambarus, linux-kernel, linux-spi, robh+dt,
	devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
	richard, cheol.yong.kim, qi-ming.wu

Hi Mark,

On 17/10/2020 12:33 am, Mark Brown wrote:
> On Fri, Oct 16, 2020 at 05:31:36PM +0800, Ramuthevar,Vadivel MuruganX wrote:
> 
>> +	depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST)
> 
>> +	{
>> +		.compatible = "intel,lgm-qspi",
>> +	},
> 
> This is an x86 SoC (or SoC series) - is it really going to use DT for
> the firmware interfaces? 
Thank you for the review comments...
Intel LGM SoC does uses DT based firmware blob.
  It's not specifically a problem, just
> surprising to see something other than ACPI.  Or is the intention to use
> PRP0001? 
Yes, You're right most of them uses ACPI based, but LGM SoC doesn't.

Regards
Vadivel
  There's a new comaptible here which wasn't really the use case
> for PRP0001.  Like I say not really a problem, just curious.
> 

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v1 1/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi
  2020-10-16  9:31 ` [PATCH v1 1/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Ramuthevar,Vadivel MuruganX
@ 2020-10-19 21:26   ` Rob Herring
  0 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-10-19 21:26 UTC (permalink / raw)
  To: Ramuthevar,Vadivel MuruganX
  Cc: simon.k.r.goldschmidt, richard, qi-ming.wu, vigneshr, linux-spi,
	broonie, robh+dt, devicetree, cheol.yong.kim, tudor.ambarus,
	miquel.raynal, dinguyen, linux-kernel

On Fri, 16 Oct 2020 17:31:33 +0800, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> 
> Move the Documentation/devicetree/bindings/mtd/cadence-quadspi.txt to
> Documentation/devicetree/bindings/spi/
> 
> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> ---
>  Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt | 0
>  1 file changed, 0 insertions(+), 0 deletions(-)
>  rename Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt (100%)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v1 2/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml
  2020-10-16  9:31 ` [PATCH v1 2/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Ramuthevar,Vadivel MuruganX
  2020-10-16 16:18   ` Mark Brown
@ 2020-10-19 21:35   ` Rob Herring
  1 sibling, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-10-19 21:35 UTC (permalink / raw)
  To: Ramuthevar,Vadivel MuruganX
  Cc: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi,
	devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
	richard, cheol.yong.kim, qi-ming.wu

On Fri, Oct 16, 2020 at 05:31:34PM +0800, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> 
> Convert the cadence-quadspi.txt documentation to cadence-quadspi.yaml
> remove the cadence-quadspi.txt from Documentation/devicetree/bindings/spi/
> 
> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> ---
>  .../devicetree/bindings/spi/cadence-quadspi.txt    |  67 ----------
>  .../devicetree/bindings/spi/cadence-quadspi.yaml   | 148 +++++++++++++++++++++
>  2 files changed, 148 insertions(+), 67 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt
>  create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
> 
> diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
> deleted file mode 100644
> index 945be7d5b236..000000000000
> --- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
> +++ /dev/null
> @@ -1,67 +0,0 @@
> -* Cadence Quad SPI controller
> -
> -Required properties:
> -- compatible : should be one of the following:
> -	Generic default - "cdns,qspi-nor".
> -	For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
> -	For TI AM654 SoC  - "ti,am654-ospi", "cdns,qspi-nor".
> -- reg : Contains two entries, each of which is a tuple consisting of a
> -	physical address and length. The first entry is the address and
> -	length of the controller register set. The second entry is the
> -	address and length of the QSPI Controller data area.
> -- interrupts : Unit interrupt specifier for the controller interrupt.
> -- clocks : phandle to the Quad SPI clock.
> -- cdns,fifo-depth : Size of the data FIFO in words.
> -- cdns,fifo-width : Bus width of the data FIFO in bytes.
> -- cdns,trigger-address : 32-bit indirect AHB trigger address.
> -
> -Optional properties:
> -- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
> -- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
> -  the read data rather than the QSPI clock. Make sure that QSPI return
> -  clock is populated on the board before using this property.
> -
> -Optional subnodes:
> -Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
> -custom properties:
> -- cdns,read-delay : Delay for read capture logic, in clock cycles
> -- cdns,tshsl-ns : Delay in nanoseconds for the length that the master
> -                  mode chip select outputs are de-asserted between
> -		  transactions.
> -- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being
> -                  de-activated and the activation of another.
> -- cdns,tchsh-ns : Delay in nanoseconds between last bit of current
> -                  transaction and deasserting the device chip select
> -		  (qspi_n_ss_out).
> -- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
> -                  and first bit transfer.
> -- resets	: Must contain an entry for each entry in reset-names.
> -		  See ../reset/reset.txt for details.
> -- reset-names	: Must include either "qspi" and/or "qspi-ocp".
> -
> -Example:
> -
> -	qspi: spi@ff705000 {
> -		compatible = "cdns,qspi-nor";
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		reg = <0xff705000 0x1000>,
> -		      <0xffa00000 0x1000>;
> -		interrupts = <0 151 4>;
> -		clocks = <&qspi_clk>;
> -		cdns,is-decoded-cs;
> -		cdns,fifo-depth = <128>;
> -		cdns,fifo-width = <4>;
> -		cdns,trigger-address = <0x00000000>;
> -		resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
> -		reset-names = "qspi", "qspi-ocp";
> -
> -		flash0: n25q00@0 {
> -			...
> -			cdns,read-delay = <4>;
> -			cdns,tshsl-ns = <50>;
> -			cdns,tsd2d-ns = <50>;
> -			cdns,tchsh-ns = <4>;
> -			cdns,tslch-ns = <4>;
> -		};
> -	};
> diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
> new file mode 100644
> index 000000000000..6ed8122a1326
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
> @@ -0,0 +1,148 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/cadence-quadspi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Cadence Quad SPI controller
> +
> +maintainers:
> +  - Vadivel Murugan <vadivel.muruganx.ramuthevar@intel.com>
> +
> +allOf:
> +  - $ref: "spi-controller.yaml#"
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: cdns,qspi-nor
> +      - const: ti,k2g-qspi, cdns,qspi-nor
> +      - const: ti,am654-ospi, cdns,qspi-nor

This says that compatible must be:

compatible = "cdns,qspi-nor", "ti,k2g-qspi, cdns,qspi-nor", "ti,am654-ospi, cdns,qspi-nor";

You need 'oneOf' here.

> +
> +    description:
> +      Should be one of the above supported compatible strings.

Drop.

> +      optional properties
> +      "cdns,is-decoded-cs" - Flag to indicate whether decoder is used or not.
> +      "cdns,rclk-en" - Flag to indicate that QSPI return clock is used to latch
> +      the read data rather than the QSPI clock. Make sure that QSPI return
> +      clock is populated on the board before using this property.

Needs to be actual schema properties.

> +
> +  reg:
> +    maxItems: 2
> +
> +    description:
> +      Contains two entries, each of which is a tuple consisting of a
> +      physical address and length. The first entry is the address and
> +      length of the controller register set. The second entry is the
> +      address and length of the QSPI Controller data area.

reg:
  items:
    - description: the controller register set
    - description: the controller data area

> +
> +  interrupts:
> +    maxItems: 1
> +    description:
> +      Unit interrupt specifier for the controller interrupt.

Drop description.

> +
> +  clocks:
> +    maxItems: 1
> +    description:
> +      phandle to the Quad SPI clock.

Drop description.

> +
> +  cdns,fifo-depth:
> +    description:
> +      Size of the data FIFO in words.
> +    allOf:

Don't need allOf here now.

> +      - $ref: "/schemas/types.yaml#/definitions/uint32"
> +      - enum: [ 128, 256 ]
> +      - default: 128
> +
> +  cdns,fifo-width:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Bus width of the data FIFO in bytes.
> +    multipleOf: 4

minimum/maximum?

> +
> +  cdns,trigger-address:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      32-bit indirect AHB trigger address.
> +
> +  resets:

How many (maxItems)?

> +     description:
> +       Must contain an entry for each entry in reset-names.
> +       See ../reset/reset.txt for details.

Drop.

> +
> +  reset-names:
> +    description:
> +      Must include either "qspi" and/or "qspi-ocp".

Needs to be schema constraints.

> +
> +# subnode's properties
> +patternProperties:
> +  "@[0-9a-f]+$":
> +    type: object
> +    description:
> +      flash device uses the subnodes below defined properties.
> +
> +  cdns,read-delay:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Delay for read capture logic, in clock cycles.
> +
> +  cdns,tshsl-ns:
> +    description: |
> +      Delay in nanoseconds for the length that the master mode chip select
> +      outputs are de-asserted between transactions.
> +
> +  cdns,tsd2d-ns:
> +    description: |
> +      Delay in nanoseconds between one chip select being de-activated
> +      and the activation of another.
> +
> +  cdns,tchsh-ns:
> +    description: |
> +      Delay in nanoseconds between last bit of current transaction and
> +      deasserting the device chip select (qspi_n_ss_out).
> +
> +  cdns,tslch-ns:
> +    description: |
> +      Delay in nanoseconds between setting qspi_n_ss_out low and
> +      first bit transfer.
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - cdns,fifo-depth
> +  - cdns,fifo-width
> +  - cdns,trigger-address
> +  - resets
> +  - reset-names

additionalProperties: false

> +
> +examples:
> +  - |
> +    qspi: spi@ff705000 {
> +      compatible = "cadence,qspi";
> +      #address-cells = <1>;
> +      #size-cells = <0>;
> +      reg = <0xff705000 0x1000>,
> +            <0xffa00000 0x1000>;
> +      interrupts = <0 151 4>;
> +      clocks = <&qspi_clk>;
> +      cdns,fifo-depth = <128>;
> +      cdns,fifo-width = <4>;
> +      cdns,trigger-address = <0x00000000>;
> +      resets = <&rst 0x1>, <&rst 0x2>;
> +      reset-names = "qspi", "qspi-ocp";
> +
> +      flash@0 {
> +              compatible = "jedec,spi-nor";
> +              reg = <0x0>;
> +              cdns,read-delay = <4>;
> +              cdns,tshsl-ns = <50>;
> +              cdns,tsd2d-ns = <50>;
> +              cdns,tchsh-ns = <4>;
> +              cdns,tslch-ns = <4>;
> +     };
> +
> +    };
> +
> +...
> -- 
> 2.11.0
> 

^ permalink raw reply	[flat|nested] 13+ messages in thread

end of thread, back to index

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-16  9:31 [PATCH v1 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-10-16  9:31 ` [PATCH v1 1/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Ramuthevar,Vadivel MuruganX
2020-10-19 21:26   ` Rob Herring
2020-10-16  9:31 ` [PATCH v1 2/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Ramuthevar,Vadivel MuruganX
2020-10-16 16:18   ` Mark Brown
2020-10-19  6:22     ` Ramuthevar, Vadivel MuruganX
2020-10-19 21:35   ` Rob Herring
2020-10-16  9:31 ` [PATCH v1 3/6] dt-bindings: spi: Add compatible for Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-10-16  9:31 ` [PATCH v1 4/6] spi: cadence-quadspi: Add QSPI support " Ramuthevar,Vadivel MuruganX
2020-10-16 16:33   ` Mark Brown
2020-10-19  6:26     ` Ramuthevar, Vadivel MuruganX
2020-10-16  9:31 ` [PATCH v1 5/6] spi: cadence-quadspi: Disable the DAC " Ramuthevar,Vadivel MuruganX
2020-10-16  9:31 ` [PATCH v1 6/6] spi: cadence-quadspi: Add multi-chipselect support " Ramuthevar,Vadivel MuruganX

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