From: Mark Brown <broonie@kernel.org>
To: "Ramuthevar,Vadivel MuruganX"
<vadivel.muruganx.ramuthevar@linux.intel.com>
Cc: vigneshr@ti.com, tudor.ambarus@microchip.com,
linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
robh+dt@kernel.org, devicetree@vger.kernel.org,
miquel.raynal@bootlin.com, simon.k.r.goldschmidt@gmail.com,
dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com,
qi-ming.wu@intel.com
Subject: Re: [PATCH v2 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
Date: Wed, 21 Oct 2020 15:46:50 +0100 [thread overview]
Message-ID: <20201021144650.GG4497@sirena.org.uk> (raw)
In-Reply-To: <20201021025507.51001-4-vadivel.muruganx.ramuthevar@linux.intel.com>
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On Wed, Oct 21, 2020 at 10:55:04AM +0800, Ramuthevar,Vadivel MuruganX wrote:
> Add multiple chipselect support for Intel LGM SoCs,
> currently QSPI-NOR and QSPI-NAND supported.
> + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT)
> + master->num_chipselect = cqspi->num_chipselect;
I'm not seeing anywhere else where we reference num_chipselect in this
patch - we parse the value, set it in the SPI controller and then never
otherwise use it? This makes me wonder if the property is really
mandatory. If it is then there should be something in the binding
document saying that it's required when the compatible is your new
compatible string, that way the validation can verify that the property
is present in DTs including this controller.
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next prev parent reply other threads:[~2020-10-21 14:47 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-21 2:55 [PATCH v2 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-10-21 2:55 ` [PATCH v2 1/6] spi: cadence-quadspi: Add QSPI " Ramuthevar,Vadivel MuruganX
2020-10-21 2:55 ` [PATCH v2 2/6] spi: cadence-quadspi: Disable the DAC " Ramuthevar,Vadivel MuruganX
2020-10-21 15:17 ` Pratyush Yadav
2020-10-22 2:17 ` Ramuthevar, Vadivel MuruganX
2020-10-22 9:01 ` Pratyush Yadav
2020-10-22 9:14 ` Ramuthevar, Vadivel MuruganX
2020-10-21 2:55 ` [PATCH v2 3/6] spi: cadence-quadspi: Add multi-chipselect support " Ramuthevar,Vadivel MuruganX
2020-10-21 14:46 ` Mark Brown [this message]
2020-10-21 15:13 ` Pratyush Yadav
2020-10-22 2:07 ` Ramuthevar, Vadivel MuruganX
2020-10-21 2:55 ` [PATCH v2 4/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Ramuthevar,Vadivel MuruganX
2020-10-21 2:55 ` [PATCH v2 5/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Ramuthevar,Vadivel MuruganX
2020-10-21 12:40 ` Mark Brown
2020-10-21 2:55 ` [PATCH v2 6/6] dt-bindings: spi: Add compatible for Intel LGM SoC Ramuthevar,Vadivel MuruganX
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