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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id b185sm2691837oif.5.2020.11.09.13.59.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2020 13:59:14 -0800 (PST) Received: (nullmailer pid 1829665 invoked by uid 1000); Mon, 09 Nov 2020 21:59:13 -0000 Date: Mon, 9 Nov 2020 15:59:13 -0600 From: Rob Herring To: Damien Le Moal Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel , Sean Anderson Subject: Re: [PATCH 15/32] dt-bindings: Define Kendryte K210 sysctl registers Message-ID: <20201109215913.GA1828781@bogus> References: <20201107081420.60325-1-damien.lemoal@wdc.com> <20201107081420.60325-16-damien.lemoal@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201107081420.60325-16-damien.lemoal@wdc.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org On Sat, Nov 07, 2020 at 05:14:03PM +0900, Damien Le Moal wrote: > Introduce the dt-bindings file include/dt-bindings/mfd/k210_sysctl.h to > define the offset of all registers of the K210 system controller. We generally don't have defines for registers in DT. > > Signed-off-by: Damien Le Moal > --- > include/dt-bindings/mfd/k210-sysctl.h | 41 +++++++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > create mode 100644 include/dt-bindings/mfd/k210-sysctl.h > > diff --git a/include/dt-bindings/mfd/k210-sysctl.h b/include/dt-bindings/mfd/k210-sysctl.h > new file mode 100644 > index 000000000000..5cc386d3c9ca > --- /dev/null > +++ b/include/dt-bindings/mfd/k210-sysctl.h > @@ -0,0 +1,41 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (C) 2020 Sean Anderson > + * Copyright (c) 2020 Western Digital Corporation or its affiliates. > + */ > +#ifndef MFD_K210_SYSCTL_H > +#define MFD_K210_SYSCTL_H > + > +/* > + * Kendryte K210 SoC system controller registers offsets. > + * Taken from Kendryte SDK (kendryte-standalone-sdk). > + */ > +#define K210_SYSCTL_GIT_ID 0x00 /* Git short commit id */ > +#define K210_SYSCTL_UART_BAUD 0x04 /* Default UARTHS baud rate */ > +#define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */ > +#define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */ > +#define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */ > +#define K210_SYSCTL_PLL_LOCK 0x18 /* PLL lock tester */ > +#define K210_SYSCTL_ROM_ERROR 0x1C /* AXI ROM detector */ > +#define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */ > +#define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */ > +#define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */ > +#define K210_SYSCTL_EN_PERI 0x2C /* Peripheral clock enable */ > +#define K210_SYSCTL_SOFT_RESET 0x30 /* Soft reset ctrl */ > +#define K210_SYSCTL_PERI_RESET 0x34 /* Peripheral reset controller */ > +#define K210_SYSCTL_THR0 0x38 /* Clock threshold controller 0 */ > +#define K210_SYSCTL_THR1 0x3C /* Clock threshold controller 1 */ > +#define K210_SYSCTL_THR2 0x40 /* Clock threshold controller 2 */ > +#define K210_SYSCTL_THR3 0x44 /* Clock threshold controller 3 */ > +#define K210_SYSCTL_THR4 0x48 /* Clock threshold controller 4 */ > +#define K210_SYSCTL_THR5 0x4C /* Clock threshold controller 5 */ > +#define K210_SYSCTL_THR6 0x50 /* Clock threshold controller 6 */ > +#define K210_SYSCTL_MISC 0x54 /* Miscellaneous controller */ > +#define K210_SYSCTL_PERI 0x58 /* Peripheral controller */ > +#define K210_SYSCTL_SPI_SLEEP 0x5C /* SPI sleep controller */ > +#define K210_SYSCTL_RESET_STAT 0x60 /* Reset source status */ > +#define K210_SYSCTL_DMA_SEL0 0x64 /* DMA handshake selector 0 */ > +#define K210_SYSCTL_DMA_SEL1 0x68 /* DMA handshake selector 1 */ > +#define K210_SYSCTL_POWER_SEL 0x6C /* IO Power Mode Select controller */ > + > +#endif /* MFD_K210_SYSCTL_H */ > -- > 2.28.0 >