From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4DD1C64E7B for ; Tue, 24 Nov 2020 04:19:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9960C20857 for ; Tue, 24 Nov 2020 04:19:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728346AbgKXES7 (ORCPT ); Mon, 23 Nov 2020 23:18:59 -0500 Received: from mga11.intel.com ([192.55.52.93]:8580 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726158AbgKXES7 (ORCPT ); Mon, 23 Nov 2020 23:18:59 -0500 IronPort-SDR: c4pbWygTXxNwyl8scjUSpfgpgsjWn7auxO62hf162uhyRAYyQeWokPHcR4VxsYW0RWuHN9MS5g 6NcjBizTgQNw== X-IronPort-AV: E=McAfee;i="6000,8403,9814"; a="168378673" X-IronPort-AV: E=Sophos;i="5.78,365,1599548400"; d="scan'208";a="168378673" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2020 20:18:58 -0800 IronPort-SDR: 6ex/SSKMnrVQveeLtw84HWt3BUKZ6ypuWaCotSwQO37Gb4REMrRVqU8pjgNHlWCoFfI1I8Mkn4 4puqfN97h0tQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,365,1599548400"; d="scan'208";a="343029861" Received: from sgsxdev004.isng.phoenix.local (HELO localhost) ([10.226.81.179]) by orsmga002.jf.intel.com with ESMTP; 23 Nov 2020 20:18:56 -0800 From: "Ramuthevar,Vadivel MuruganX" To: broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: linux-mtd@lists.infradead.org, vigneshr@ti.com, p.yadav@ti.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v9 3/5] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC Date: Tue, 24 Nov 2020 12:18:38 +0800 Message-Id: <20201124041840.31066-4-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Add multiple chipselect support for Intel LGM SoCs, currently QSPI-NOR and QSPI-NAND supported. Signed-off-by: Ramuthevar Vadivel Murugan --- drivers/spi/spi-cadence-quadspi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index d12b765e87be..c7ecd6d44326 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -75,6 +75,7 @@ struct cqspi_st { bool is_decoded_cs; u32 fifo_depth; u32 fifo_width; + u32 num_chipselect; bool rclk_en; u32 trigger_address; u32 wr_delay; @@ -1070,6 +1071,9 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi) return -ENXIO; } + if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) + cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; + cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); return 0; @@ -1302,6 +1306,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->current_cs = -1; cqspi->sclk = 0; + master->num_chipselect = cqspi->num_chipselect; + ret = cqspi_setup_flash(cqspi); if (ret) { dev_err(dev, "failed to setup flash parameters %d\n", ret); -- 2.11.0