Default configuration for CS-to-SCK/SCK-to-CS delays

Default configuration for CS-to-SCK/SCK-to-CS delays

[Vladimir Oltean]

Hi,

The spi-fsl-dspi.c driver has two device tree properties per child node:
- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
  select and the start of clock signal, at the start of a transfer.
- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
  signal and deactivating chip select, at the end of a transfer.

Some people are complaining about the fact that when these properties
are missing, the DSPI controller will use zero delay values with that
specific SPI slave. This is particularly relevant when the SPI slave
driver is spidev, so you don't know exactly what is connected.

I tried to search for "delay" under drivers/spi/, but I am not exactly
edified as to what other drivers do to solve this problem. For example,
a SPI-connected Ethernet switch I am working with does explicitly say in
the datasheet that "after the CS signal has been asserted at the
beginning of an SPI read or write operation, the SPI clock signal
(SCK) must be stable for at least 0.5 x t_clk before being asserted".
Many more peripherals may have similar requirements, but I'm not sure
that there is any universal formula. Hence the question: is there any
default configuration that the driver can perform in order to avoid
having to put it in device tree?

Thanks,
-Vladimir

Re: Default configuration for CS-to-SCK/SCK-to-CS delays

[Mark Brown]

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On Thu, Apr 08, 2021 at 12:45:48PM +0300, Vladimir Oltean wrote:

> that there is any universal formula. Hence the question: is there any
> default configuration that the driver can perform in order to avoid
> having to put it in device tree?

Something broadly proportional to the clock rate/peroid for the bus is
probably going to work most of the time.

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