From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E904EC433FE for ; Fri, 11 Mar 2022 08:01:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346684AbiCKIDA (ORCPT ); Fri, 11 Mar 2022 03:03:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240698AbiCKIDA (ORCPT ); Fri, 11 Mar 2022 03:03:00 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6EB91B84E7; Fri, 11 Mar 2022 00:01:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646985718; x=1678521718; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0tEtyDy2Ibn+Yb9/V/d4TdD6beKGnXWWbYrC9P89cv4=; b=mm4qE3zBR3v9d0VJoztFToE1nMjaEriWWrKTWNqYSSeefE7Og7EzElpR OajmJl8gfSUCGOgqnVV72NImKHY/yf7cJo5zvl7YhymTGcA16CCb2x2jA wVqWXL3T3p8NL0r3PuszcbCKUpW9Sz8n7L7QoVJL4rJC7MZSL8vXU8jku 8D64szr1nZn3vC571PfQxQAhaQUefHgJCknOi9nC3PEtB0mgNN5dWmMLm uQKDP5ICZ4PmOJsiH/JeVRJChpAYKbGF6f/DOUNQXOtFQLOfT5rMPj+7L G+FJyLgrvGquKHvUfw5YaU2ygcvWuoeMfyWuN2UfICl5AJV/GcghIgbOu g==; X-IronPort-AV: E=Sophos;i="5.90,173,1643698800"; d="scan'208";a="148864914" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Mar 2022 01:01:57 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 11 Mar 2022 01:01:56 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 11 Mar 2022 01:01:53 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH v2 1/6] spi: spi-mem: Allow specifying the byte order in DTR mode Date: Fri, 11 Mar 2022 10:01:42 +0200 Message-ID: <20220311080147.453483-2-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311080147.453483-1-tudor.ambarus@microchip.com> References: <20220311080147.453483-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org There are NOR flashes (Macronix) that swap the bytes on a 16-bit boundary when configured in Octal DTR mode. The byte order of 16-bit words is swapped when read or written in Octal Double Transfer Rate (DTR) mode compared to Single Transfer Rate (STR) modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses 8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2. Swapping the bytes is a bad design decision because it may introduce some endianness problems. It can affect the boot sequence if the entire boot sequence is not handled in either 8D-8D-8D mode or 1-1-1 mode. So we must swap the bytes back to have the same byte order as in STR modes. Fortunately there are controllers that can swap the bytes back at runtime, addressing the flash's endiannesses requirements. Provide a way for the upper layers to specify the byte order in Octal DTR mode. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-mem.c | 4 ++++ include/linux/spi/spi-mem.h | 6 ++++++ 2 files changed, 10 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index f38ac31961c9..3b2e586bb6a6 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -171,6 +171,10 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, if (!spi_mem_controller_is_capable(ctlr, dtr)) return false; + if (op->data.dtr_swab16 && + !(spi_mem_controller_is_capable(ctlr, dtr_swab16))) + return false; + if (op->cmd.nbytes != 2) return false; } else { diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 2ba044d0d5e5..a1bf51eda31f 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -89,6 +89,8 @@ enum spi_mem_data_dir { * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not * @data.buswidth: number of IO lanes used to send/receive the data * @data.dtr: whether the data should be sent in DTR mode or not + * @data.dtr_swab16: whether the byte order of 16-bit words is swapped when read + * or written in Octal DTR mode compared to STR mode. * @data.ecc: whether error correction is required or not * @data.dir: direction of the transfer * @data.nbytes: number of data bytes to send/receive. Can be zero if the @@ -120,6 +122,7 @@ struct spi_mem_op { struct { u8 buswidth; u8 dtr : 1; + u8 dtr_swab16 : 1; u8 ecc : 1; enum spi_mem_data_dir dir; unsigned int nbytes; @@ -290,10 +293,13 @@ struct spi_controller_mem_ops { /** * struct spi_controller_mem_caps - SPI memory controller capabilities * @dtr: Supports DTR operations + * @dtr_swab16: Supports swapping bytes on a 16 bit boundary when configured in + * Octal DTR * @ecc: Supports operations with error correction */ struct spi_controller_mem_caps { bool dtr; + bool dtr_swab16; bool ecc; }; -- 2.25.1