From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Behme Dirk (CM/ESO2)" Subject: Re: [PATCH RFC 2/2] memory: add Renesas RPC-IF driver Date: Tue, 25 Feb 2020 10:33:10 +0100 Message-ID: <3a182ac7-8d41-cdc7-2b87-7c503f68a426@de.bosch.com> References: <4db876ed-1ccc-e3be-311d-30cd52f40259@cogentembedded.com> <5760bcdb-e44b-6f18-7262-9526684e5780@de.bosch.com> <5603f393-554d-e2a8-c2d8-6bafc20f4169@cogentembedded.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------A266F512431D32413D4D0BF3" Cc: , , Philipp Zabel , Mason Yang , , Chris Brandt , To: Sergei Shtylyov Return-path: In-Reply-To: Content-Language: en-US Sender: linux-renesas-soc-owner@vger.kernel.org List-Id: linux-spi.vger.kernel.org --------------A266F512431D32413D4D0BF3 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit On 24.02.2020 19:59, Sergei Shtylyov wrote: >>>> From d72b805cc461ab1e9747c973e9be84e7abb8f828 Mon Sep 17 00:00:00 2001 >>>> From: Dirk Behme >>>> Date: Tue, 4 Feb 2020 08:39:31 +0100 >>>> Subject: [PATCH] memory: renesas-rpc-if: Correct the STRTIM and some other >>>> clean up >>>> >>>> This is required to make the driver work correctly in my M3 environment. >>>> >>>> Signed-off-by: Dirk Behme >>>> --- >>>> drivers/memory/renesas-rpc-if.c | 42 ++++++++++++++++++++------------- >>>> 1 file changed, 25 insertions(+), 17 deletions(-) >>>> >>>> diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c >>>> index 04be92b64bfa..f4356b066384 100644 >>>> --- a/drivers/memory/renesas-rpc-if.c >>>> +++ b/drivers/memory/renesas-rpc-if.c >>> [...] >>>> @@ -513,19 +525,15 @@ ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf) >>>> pm_runtime_get_sync(rpc->dev); >>>> >>>> regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0); >>>> - regmap_write(rpc->regmap, RPCIF_DRCR, >>>> - RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE); >>>> - regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command); >>>> - regmap_write(rpc->regmap, RPCIF_DREAR, >>>> - RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1)); >>>> - regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option); >>>> - regmap_write(rpc->regmap, RPCIF_DRENR, >>>> - rpc->enable & ~RPCIF_SMENR_SPIDE(0xF)); >>>> - regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy); >>>> - regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr); >>> >>> The driver somehow works only with this left in place (with 2 bytes eaten >>> as before), otherwise all the flash reads all 0xff (via dirmap). >> >> >> Do you boot from hyperflash? > > No, I have arewto say 'cpld write 30 1' in U-Boot before a boot a kernel. > Normally, the V3x Starter Kit boards are wired for the QSPI flash chips. > >> The system I'm using for testing boots from hyperflash. So most probably all registers >> I don't touch in the driver are put into a reasonable state by the boot code, already. >> If you don't boot from hyperflash, that at least would explain our different behavior. > > Yes. Mind dumping the registers and sending to me? Using the attached debug patch (0001-memory-renesas-rpc-if-DEBUG-Dump-register-content.patch) on a r8a7796 system booting from Hyperflash with above register dropping reverted (i.e. including touching these registers) I get Before: RPCIF_DRCR: 0x00000000 RPCIF_DRCMR: 0x00a00000 RPCIF_DREAR: 0x00000000 RPCIF_DROPR: 0x00000000 RPCIF_DRENR: 0xa222d400 RPCIF_DRDMCR: 0x0000000e RPCIF_DRDRENR: 0x00005101 After: RPCIF_DRCR: 0x001f0100 RPCIF_DRCMR: 0x00a00000 RPCIF_DREAR: 0x00010001 RPCIF_DROPR: 0x00000000 RPCIF_DRENR: 0xa202d400 RPCIF_DRDMCR: 0x0000000e RPCIF_DRDRENR: 0x00005101 Comparing that, just 3 registers are different between my working version ("Before") and the version which shows the 2-byte offset ("After"): RPCIF_DRCR, RPCIF_DREAR and RPCIF_DRENR. With try & error, at least in my setup, I was able to reduce this to just RPCIF_DRCR. Dropping the burst mode I was able to 'fix' the two byte offset issue. Do you like to give the attached 0001-memory-renesas-rpc-if-Don-t-use-burst-mode-on-read.patch a try in your setup? Best regards Dirk --------------A266F512431D32413D4D0BF3 Content-Type: text/plain; charset="UTF-8"; name="0001-memory-renesas-rpc-if-DEBUG-Dump-register-content.patch" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="0001-memory-renesas-rpc-if-DEBUG-Dump-register-content.patch" RnJvbSA4OTQyYzc3MWY4ZWE4OTU3YTE0ZmM2ZjZlNDQ0MzY3NWM0YjZiMjYwIE1vbiBTZXAg MTcgMDA6MDA6MDAgMjAwMQpGcm9tOiBEaXJrIEJlaG1lIDxkaXJrLmJlaG1lQGRlLmJvc2No LmNvbT4KRGF0ZTogVHVlLCAyNSBGZWIgMjAyMCAwNzo1NzoxMiArMDEwMApTdWJqZWN0OiBb UEFUQ0hdIG1lbW9yeTogcmVuZXNhcy1ycGMtaWY6IERFQlVHOiBEdW1wIHJlZ2lzdGVyIGNv bnRlbnQKCkR1bXAgcmVnaXN0ZXIgY29udGVudCBiZWZvcmUgYW5kIGFmdGVyIGJlaW5nIG1v ZGlmaWVkIGJ5IHRoZSBkcml2ZXIuCgpTaWduZWQtb2ZmLWJ5OiBEaXJrIEJlaG1lIDxkaXJr LmJlaG1lQGRlLmJvc2NoLmNvbT4KLS0tCiBkcml2ZXJzL21lbW9yeS9yZW5lc2FzLXJwYy1p Zi5jIHwgMjEgKysrKysrKysrKysrKysrKysrKysrCiAxIGZpbGUgY2hhbmdlZCwgMjEgaW5z ZXJ0aW9ucygrKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvbWVtb3J5L3JlbmVzYXMtcnBjLWlm LmMgYi9kcml2ZXJzL21lbW9yeS9yZW5lc2FzLXJwYy1pZi5jCmluZGV4IDQ4NTNlN2Y3ODk4 NS4uNDQ4NmRlMGI1MTdiIDEwMDY0NAotLS0gYS9kcml2ZXJzL21lbW9yeS9yZW5lc2FzLXJw Yy1pZi5jCisrKyBiL2RyaXZlcnMvbWVtb3J5L3JlbmVzYXMtcnBjLWlmLmMKQEAgLTUxNywx MiArNTE3LDIzIEBAIHNzaXplX3QgcnBjaWZfZGlybWFwX3JlYWQoc3RydWN0IHJwY2lmICpy cGMsIHU2NCBvZmZzLCBzaXplX3QgbGVuLCB2b2lkICpidWYpCiB7CiAJbG9mZl90IGZyb20g PSBvZmZzICYgKFJQQ0lGX0RJUk1BUF9TSVpFIC0gMSk7CiAJc2l6ZV90IHNpemUgPSBSUENJ Rl9ESVJNQVBfU0laRSAtIGZyb207CisJdTMyIGRhdGE7CiAKIAlpZiAobGVuID4gc2l6ZSkK IAkJbGVuID0gc2l6ZTsKIAogCXBtX3J1bnRpbWVfZ2V0X3N5bmMocnBjLT5kZXYpOwogCisJ cHJfZXJyKCJCZWZvcmU6XG4iKTsKKwlyZWdtYXBfcmVhZChycGMtPnJlZ21hcCwgUlBDSUZf Q01OQ1IsICZkYXRhKTsgICBwcl9lcnIoIlJQQ0lGX0NNTkNSOiAgIDB4JTA4eFxuIiwgZGF0 YSk7CisJcmVnbWFwX3JlYWQocnBjLT5yZWdtYXAsIFJQQ0lGX0RSQ1IsICZkYXRhKTsgICAg cHJfZXJyKCJSUENJRl9EUkNSOiAgICAweCUwOHhcbiIsIGRhdGEpOworCXJlZ21hcF9yZWFk KHJwYy0+cmVnbWFwLCBSUENJRl9EUkNNUiwgJmRhdGEpOyAgIHByX2VycigiUlBDSUZfRFJD TVI6ICAgMHglMDh4XG4iLCBkYXRhKTsKKwlyZWdtYXBfcmVhZChycGMtPnJlZ21hcCwgUlBD SUZfRFJFQVIsICZkYXRhKTsgICBwcl9lcnIoIlJQQ0lGX0RSRUFSOiAgIDB4JTA4eFxuIiwg ZGF0YSk7CisJcmVnbWFwX3JlYWQocnBjLT5yZWdtYXAsIFJQQ0lGX0RST1BSLCAmZGF0YSk7 ICAgcHJfZXJyKCJSUENJRl9EUk9QUjogICAweCUwOHhcbiIsIGRhdGEpOworCXJlZ21hcF9y ZWFkKHJwYy0+cmVnbWFwLCBSUENJRl9EUkVOUiwgJmRhdGEpOyAgIHByX2VycigiUlBDSUZf RFJFTlI6ICAgMHglMDh4XG4iLCBkYXRhKTsKKwlyZWdtYXBfcmVhZChycGMtPnJlZ21hcCwg UlBDSUZfRFJETUNSLCAmZGF0YSk7ICBwcl9lcnIoIlJQQ0lGX0RSRE1DUjogIDB4JTA4eFxu IiwgZGF0YSk7CisJcmVnbWFwX3JlYWQocnBjLT5yZWdtYXAsIFJQQ0lGX0RSRFJFTlIsICZk YXRhKTsgcHJfZXJyKCJSUENJRl9EUkRSRU5SOiAweCUwOHhcbiIsIGRhdGEpOworCiAJcmVn bWFwX3VwZGF0ZV9iaXRzKHJwYy0+cmVnbWFwLCBSUENJRl9DTU5DUiwgUlBDSUZfQ01OQ1Jf TUQsIDApOwogCXJlZ21hcF93cml0ZShycGMtPnJlZ21hcCwgUlBDSUZfRFJDUiwKIAkJICAg ICBSUENJRl9EUkNSX1JCVVJTVCgzMikgfCBSUENJRl9EUkNSX1JCRSk7CkBAIC01MzUsNiAr NTQ2LDE2IEBAIHNzaXplX3QgcnBjaWZfZGlybWFwX3JlYWQoc3RydWN0IHJwY2lmICpycGMs IHU2NCBvZmZzLCBzaXplX3QgbGVuLCB2b2lkICpidWYpCiAJcmVnbWFwX3dyaXRlKHJwYy0+ cmVnbWFwLCBSUENJRl9EUkRNQ1IsIHJwYy0+ZHVtbXkpOwogCXJlZ21hcF93cml0ZShycGMt PnJlZ21hcCwgUlBDSUZfRFJEUkVOUiwgcnBjLT5kZHIpOwogCisJcHJfZXJyKCJBZnRlcjpc biIpOworCXJlZ21hcF9yZWFkKHJwYy0+cmVnbWFwLCBSUENJRl9DTU5DUiwgJmRhdGEpOyAg IHByX2VycigiUlBDSUZfQ01OQ1I6ICAgMHglMDh4XG4iLCBkYXRhKTsKKwlyZWdtYXBfcmVh ZChycGMtPnJlZ21hcCwgUlBDSUZfRFJDUiwgJmRhdGEpOyAgICBwcl9lcnIoIlJQQ0lGX0RS Q1I6ICAgIDB4JTA4eFxuIiwgZGF0YSk7CisJcmVnbWFwX3JlYWQocnBjLT5yZWdtYXAsIFJQ Q0lGX0RSQ01SLCAmZGF0YSk7ICAgcHJfZXJyKCJSUENJRl9EUkNNUjogICAweCUwOHhcbiIs IGRhdGEpOworCXJlZ21hcF9yZWFkKHJwYy0+cmVnbWFwLCBSUENJRl9EUkVBUiwgJmRhdGEp OyAgIHByX2VycigiUlBDSUZfRFJFQVI6ICAgMHglMDh4XG4iLCBkYXRhKTsKKwlyZWdtYXBf cmVhZChycGMtPnJlZ21hcCwgUlBDSUZfRFJPUFIsICZkYXRhKTsgICBwcl9lcnIoIlJQQ0lG X0RST1BSOiAgIDB4JTA4eFxuIiwgZGF0YSk7CisJcmVnbWFwX3JlYWQocnBjLT5yZWdtYXAs IFJQQ0lGX0RSRU5SLCAmZGF0YSk7ICAgcHJfZXJyKCJSUENJRl9EUkVOUjogICAweCUwOHhc biIsIGRhdGEpOworCXJlZ21hcF9yZWFkKHJwYy0+cmVnbWFwLCBSUENJRl9EUkRNQ1IsICZk YXRhKTsgIHByX2VycigiUlBDSUZfRFJETUNSOiAgMHglMDh4XG4iLCBkYXRhKTsKKwlyZWdt YXBfcmVhZChycGMtPnJlZ21hcCwgUlBDSUZfRFJEUkVOUiwgJmRhdGEpOyBwcl9lcnIoIlJQ Q0lGX0RSRFJFTlI6IDB4JTA4eFxuIiwgZGF0YSk7CisKIAltZW1jcHlfZnJvbWlvKGJ1Ziwg cnBjLT5kaXJtYXAgKyBmcm9tLCBsZW4pOwogCiAJcG1fcnVudGltZV9wdXQocnBjLT5kZXYp OwotLSAKMi4yMC4wCgo= --------------A266F512431D32413D4D0BF3 Content-Type: text/plain; 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