From: Michael Walle <michael@walle.cc>
To: Tudor Ambarus <tudor.ambarus@microchip.com>
Cc: p.yadav@ti.com, broonie@kernel.org, miquel.raynal@bootlin.com,
richard@nod.at, vigneshr@ti.com, linux-mtd@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
nicolas.ferre@microchip.com, zhengxunli@mxic.com.tw,
jaimeliao@mxic.com.tw
Subject: Re: [PATCH 0/4] spi-mem: Allow specifying the byte order in DTR mode
Date: Mon, 21 Feb 2022 08:44:35 +0100 [thread overview]
Message-ID: <44f655d027b49b87065915f6ba2744d2@walle.cc> (raw)
In-Reply-To: <20220218145900.1440045-1-tudor.ambarus@microchip.com>
Am 2022-02-18 15:58, schrieb Tudor Ambarus:
> Fortunately there are controllers
> that can swap back the bytes at runtime, fixing the endiannesses.
> Provide
> a way for the upper layers to specify the byte order in DTR mode.
Are there any patches for the atmel-quadspi yet? What happens if
the controller doesn't support it? Will there be a software fallback?
-michael
next prev parent reply other threads:[~2022-02-21 7:44 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-18 14:58 [PATCH 0/4] spi-mem: Allow specifying the byte order in DTR mode Tudor Ambarus
2022-02-18 14:58 ` [PATCH 1/4] spi: " Tudor Ambarus
2022-03-02 10:02 ` Pratyush Yadav
2022-03-10 5:31 ` Tudor.Ambarus
2022-03-11 17:47 ` Pratyush Yadav
2022-02-18 14:58 ` [PATCH 2/4] mtd: spi-nor: core: " Tudor Ambarus
2022-02-21 7:36 ` Michael Walle
2022-02-22 14:02 ` Tudor.Ambarus
2022-02-22 14:23 ` Michael Walle
2022-03-02 11:34 ` Pratyush Yadav
2022-03-10 8:54 ` Tudor.Ambarus
2022-02-18 14:58 ` [PATCH 3/4] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT Tudor Ambarus
2022-02-21 7:40 ` Michael Walle
2022-03-02 12:28 ` Pratyush Yadav
2022-02-18 14:59 ` [PATCH 4/4] mtd: spi-nor: core: Introduce SPI_NOR_DTR_BSWAP16 no_sfdp_flag Tudor Ambarus
2022-02-21 7:41 ` Michael Walle
2022-03-02 12:30 ` Pratyush Yadav
2022-03-10 4:42 ` Tudor.Ambarus
2022-02-21 7:44 ` Michael Walle [this message]
2022-02-22 13:54 ` [PATCH 0/4] spi-mem: Allow specifying the byte order in DTR mode Tudor.Ambarus
2022-02-22 14:13 ` Michael Walle
2022-02-22 14:23 ` Tudor.Ambarus
2022-02-22 14:27 ` Michael Walle
2022-02-22 14:43 ` Tudor.Ambarus
2022-02-23 18:38 ` Pratyush Yadav
2022-02-24 6:08 ` Tudor.Ambarus
2022-02-24 6:37 ` Tudor.Ambarus
2022-02-24 9:37 ` Michael Walle
2022-02-24 10:27 ` Tudor.Ambarus
2022-02-25 7:35 ` zhengxunli
2022-02-24 13:24 ` Pratyush Yadav
2022-02-24 14:02 ` Michael Walle
2022-02-24 14:33 ` Tudor.Ambarus
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