diff --git a/drivers/spi/mpc52xx_psc_spi.c b/drivers/spi/mpc52xx_psc_spi.c
index 1b74d5c..b15882a 100644
--- a/drivers/spi/mpc52xx_psc_spi.c
+++ b/drivers/spi/mpc52xx_psc_spi.c
@@ -78,7 +78,8 @@ static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
 	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 	struct mpc52xx_psc __iomem *psc = mps->psc;
 	u32 sicr;
-	u16 ccr;
+	u32 ccr;
+	u32 bitclkdiv;
 
 	sicr = in_be32(&psc->sicr);
 
@@ -98,17 +99,16 @@ static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
 		sicr &= ~0x10000000;
 	out_be32(&psc->sicr, sicr);
 
-	/* Set clock frequency and bits per word
-	 * Because psc->ccr is defined as 16bit register instead of 32bit
-	 * just set the lower byte of BitClkDiv
-	 */
-	ccr = in_be16((u16 __iomem *)&psc->ccr);
-	ccr &= 0xFF00;
-	if (cs->speed_hz)
-		ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
-	else /* by default SPI Clk 1MHz */
-		ccr |= (MCLK / 1000000 - 1) & 0xFF;
-	out_be16((u16 __iomem *)&psc->ccr, ccr);
+	/* Set clock frequency */
+	bitclkdiv = MCLK / (cs->speed_hz ? cs->speed_hz : 1000000) - 1;
+	bitclkdiv &= 0xFFFF;
+	bitclkdiv |= (bitclkdiv & 0xFF) << 16;	/* byte swapped */
+	bitclkdiv &= 0x00FFFF00;
+	ccr = in_be32(&psc->ccr);
+	ccr &= 0xFF0000FF;
+	ccr |= bitclkdiv;
+	out_be32(&psc->ccr, ccr);
+	
 	mps->bits_per_word = cs->bits_per_word;
 
 	if (mps->cs_control)
@@ -333,7 +333,7 @@ static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
 	/* Configure 8bit codec mode as a SPI master and use EOF flags */
 	/* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
 	out_be32(&psc->sicr, 0x0180C800);
-	out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
+	out_be32(&psc->ccr, 0x07130000); /* default SPI Clk 1MHz */
 
 	/* Set 2ms DTL delay */
 	out_8(&psc->ctur, 0x00);