From: Christophe Leroy <christophe.leroy-GgN8y9CXRhA@public.gmane.org>
To: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
linux-spi <linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: How to handle SPI components requiring heading/leading clock cycles with CS off
Date: Tue, 23 Aug 2016 18:10:48 +0200 [thread overview]
Message-ID: <79679118-c092-1f9c-1972-0bb81bc59411@c-s.fr> (raw)
Some components requires some clock cycles with chipselect off before
or/and after the data transfer done with CS on.
Typically IDT801034 QUAD PCM CODEC datasheet states "Note *: CCLK should
have one cycle before CS goes low, and two cycles after CS goes high".
The only way I see to achieve that is to transfer a 4 bits word with CS
off before and after the data.
I've not found any way to do so in the current SPI subsystem
implementation, is there any ?
If not, what would be the best approach to implement that ?
Cheers,
Christophe
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next reply other threads:[~2016-08-23 16:10 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-23 16:10 Christophe Leroy [this message]
[not found] ` <79679118-c092-1f9c-1972-0bb81bc59411-GgN8y9CXRhA@public.gmane.org>
2016-08-24 9:44 ` How to handle SPI components requiring heading/leading clock cycles with CS off Mark Brown
[not found] ` <20160824094456.GB22076-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2016-08-24 10:49 ` Christophe Leroy
[not found] ` <8c6cbd99-7dd8-bbbf-89ee-a33752ab3063-GgN8y9CXRhA@public.gmane.org>
2016-08-24 10:56 ` Mark Brown
[not found] ` <20160824105640.GC22076-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2016-08-24 11:03 ` Christophe Leroy
[not found] ` <15444613-2f3d-9417-7d81-e545058afdf0-GgN8y9CXRhA@public.gmane.org>
2016-08-24 11:12 ` Mark Brown
[not found] ` <20160824111206.GD22076-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2016-08-24 11:19 ` Christophe Leroy
[not found] ` <9e854e9d-146c-61ea-da6e-a46b316b56c5-GgN8y9CXRhA@public.gmane.org>
2016-08-24 11:27 ` Mark Brown
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