From: Lars Povlsen <lars.povlsen@microchip.com>
To: Mark Brown <broonie@kernel.org>
Cc: Lars Povlsen <lars.povlsen@microchip.com>,
SoC Team <soc@kernel.org>,
Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
<linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
"Serge Semin" <fancer.lancer@gmail.com>,
Serge Semin <Sergey.Semin@baikalelectronics.ru>
Subject: Re: [PATCH v2 3/6] spi: dw: Add Microchip Sparx5 support
Date: Mon, 22 Jun 2020 12:46:33 +0200 [thread overview]
Message-ID: <87imfjxtrq.fsf@soft-dev15.microsemi.net> (raw)
In-Reply-To: <20200619121107.GE5396@sirena.org.uk>
Mark Brown writes:
On Fri, Jun 19, 2020 at 01:31:18PM +0200, Lars Povlsen wrote:
>> +/*
>> + * The Designware SPI controller (referred to as master in the
>> + * documentation) automatically deasserts chip select when the tx fifo
>> + * is empty. The chip selects then needs to be driven by a CS override
>> + * register. enable is an active low signal.
>> + */
>> +static void dw_spi_sparx5_set_cs(struct spi_device *spi, bool nEnable)
>
>The value that is passed in here is the value that should be driven on
>the output pin, the driver should not be interpreting the value in any
>way here. Documenting it as nEnable adds a layer of confusion, and it
>may not be an active high signal depending on the system.
Ok, I will make the CS function more like the others.
>
>> + if (!nEnable) {
>> + /* Ensure CS toggles, so start off all disabled */
>> + regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~0);
>> + /* CS override drive enable */
>> + regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 1);
>
>This should just be setting the value to whatever the core asked for it
>to be set to, the driver adding extra toggles is likely to disrupt
>things.
I will have a look at this again. But it was added for a reason. The
issue is that we have two different busses in front of the controller,
so we might need more settle time when switching interface.
Thank you for you comments,
Cheers
--
Lars Povlsen,
Microchip
next prev parent reply other threads:[~2020-06-22 10:46 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-19 11:31 [PATCH v2 0/6] spi: Adding support for Microchip Sparx5 SoC Lars Povlsen
2020-06-19 11:31 ` [PATCH v2 1/6] spi: dw: Add support for RX sample delay register Lars Povlsen
2020-06-19 11:31 ` [PATCH v2 2/6] arm64: dts: sparx5: Add SPI controller Lars Povlsen
2020-06-19 11:31 ` [PATCH v2 3/6] spi: dw: Add Microchip Sparx5 support Lars Povlsen
[not found] ` <20200619121107.GE5396@sirena.org.uk>
2020-06-22 10:46 ` Lars Povlsen [this message]
[not found] ` <20200622121706.GF4560@sirena.org.uk>
2020-06-23 13:53 ` Lars Povlsen
2020-06-23 14:08 ` Mark Brown
2020-07-02 10:05 ` Lars Povlsen
2020-06-19 11:31 ` [PATCH v2 4/6] dt-bindings: snps,dw-apb-ssi: Add sparx5, SPI slave snps,rx-sample-delay-ns and microchip,spi-interface2 properties Lars Povlsen
2020-06-19 11:31 ` [PATCH v2 5/6] arm64: dts: sparx5: Add spi-nor support Lars Povlsen
2020-06-19 11:31 ` [PATCH v2 6/6] arm64: dts: sparx5: Add spi-nand devices Lars Povlsen
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