From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Ramuthevar, Vadivel MuruganX"
        <vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Subject: Re: [PATCH v10 1/2] dt-bindings: spi: Add schema for Cadence QSPI
 Controller driver
Date: Wed, 26 Feb 2020 09:32:31 +0800
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To: Vignesh Raghavendra <vigneshr-l0cyMroinI0@public.gmane.org>,
        Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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Hi,

On 25/2/2020 7:00 PM, Vignesh Raghavendra wrote:
>
> On 25/02/20 1:08 pm, Ramuthevar, Vadivel MuruganX wrote:
>>>>>> +
>>>>>> +  cdns,fifo-depth:
>>>>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>>>>> +    description:
>>>>>> +      Size of the data FIFO in words.
>>>>> A 4GB fifo is valid? Add some constraints.
>>>> 128 is valid, will update.
>>> Nope, the width of this field is 8bits -> 256 bytes
>> correct me if I am wrong, the width of this field is 4bits -> 128 bytes
>> (based on QUAD mode) .
> This has nothing to do with quad-mode. Its about how much SRAM amount of
> SRAM is present to buffer INDAC mode data. For TI platforms this is 256
> bytes.
> See CQSPI_REG_SRAMPARTITION definition in your datasheet.
Agreed, Thanks!
Yes , I have gone through it , Intel and Altera SoC's SRAM(act as 
FIFO)size is 128 bytes and TI has 256 .
BTW old legacy DT binding mentioned size is 128, as per your earlier 
suggestion you have mention that
keep the contents from old dt bindings as it is, so shall I keep 128/256?

Regards
Vadivel