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[209.85.221.44]) by smtp.gmail.com with ESMTPSA id u10sm2672186edo.14.2020.08.22.07.52.54 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 22 Aug 2020 07:52:55 -0700 (PDT) Received: by mail-wr1-f44.google.com with SMTP id d16so4505855wrq.9 for ; Sat, 22 Aug 2020 07:52:54 -0700 (PDT) X-Received: by 2002:a5d:6744:: with SMTP id l4mr7904439wrw.105.1598107973784; Sat, 22 Aug 2020 07:52:53 -0700 (PDT) MIME-Version: 1.0 References: <20200821161401.11307-1-l.stelmach@samsung.com> <20200821161401.11307-8-l.stelmach@samsung.com> <20200822124325.GF20423@kozik-lap> In-Reply-To: <20200822124325.GF20423@kozik-lap> From: Tomasz Figa Date: Sat, 22 Aug 2020 16:52:40 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 7/9] spi: spi-s3c64xx: Ensure cur_speed holds actual clock value To: Krzysztof Kozlowski Cc: =?UTF-8?Q?=C5=81ukasz_Stelmach?= , Kukjin Kim , Andi Shyti , Mark Brown , linux-spi@vger.kernel.org, linux-samsung-soc , "list@263.net:IOMMU DRIVERS , Joerg Roedel ," , Linux Kernel Mailing List , Marek Szyprowski , Bartlomiej Zolnierkiewicz Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org On Sat, Aug 22, 2020 at 2:43 PM Krzysztof Kozlowski wrote= : > > On Fri, Aug 21, 2020 at 06:13:59PM +0200, =C5=81ukasz Stelmach wrote: > > cur_speed is used to calculate transfer timeout and needs to be > > set to the actual value of (half) the clock speed for precise > > calculations. > > If you need this only for timeout calculation just divide it in > s3c64xx_wait_for_dma(). Division is not the point of the patch. The point is that clk_set_rate() that was originally there doesn't guarantee that the rate is set exactly. The rate directly determines the SPI transfer speed and thus the driver needs to use the rate that was actually set for further calculations. > Otherwise why only if (cmu) case is updated? Right, the !cmu case actually suffers from the same problem. The code divides the parent clock rate with the requested speed to obtain the divider to program into the register. This is subject to integer rounding, so (parent / (parent / speed)) doesn't always equal (speed). > > You are also affecting here not only timeout but > s3c64xx_enable_datapath() which is not mentioned in commit log. In other > words, this looks wrong. Actually this is right and fixes one more problem, which I didn't spot when looking at this code when I suggested the change (I only spotted the effects on timeout calculation). The rounding error might have caused wrong configuration there, because e.g. 30000000 Hz could be requested and rounded to 28000000 Hz. The former is a threshold for setting the S3C64XX_SPI_CH_HS_EN bit, but the real frequency wouldn't actually require setting it. Best regards, Tomasz > > Best regards, > Krzysztof > > > > > Cc: Tomasz Figa > > Signed-off-by: =C5=81ukasz Stelmach > > --- > > drivers/spi/spi-s3c64xx.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c > > index 02de734b8ab1..89c162efe355 100644 > > --- a/drivers/spi/spi-s3c64xx.c > > +++ b/drivers/spi/spi-s3c64xx.c > > @@ -626,6 +626,7 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_dr= iver_data *sdd) > > ret =3D clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); > > if (ret) > > return ret; > > + sdd->cur_speed =3D clk_get_rate(sdd->src_clk) / 2; > > } else { > > /* Configure Clock */ > > val =3D readl(regs + S3C64XX_SPI_CLK_CFG); > > -- > > 2.26.2 > >