From: Andy Shevchenko <andy.shevchenko@gmail.com>
To: Lars Povlsen <lars.povlsen@microchip.com>
Cc: Mark Brown <broonie@kernel.org>, SoC Team <soc@kernel.org>,
Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
linux-spi <linux-spi@vger.kernel.org>,
devicetree <devicetree@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>,
Alexandre Belloni <alexandre.belloni@bootlin.com>
Subject: Re: [PATCH 01/10] spi: dw: Add support for polled operation via no IRQ specified in DT
Date: Wed, 13 May 2020 17:55:50 +0300 [thread overview]
Message-ID: <CAHp75VcA-oDboufsDNx1ZR4+HBwYt7LdLOpbfs7-bM9ByucKJA@mail.gmail.com> (raw)
In-Reply-To: <20200513140031.25633-2-lars.povlsen@microchip.com>
On Wed, May 13, 2020 at 5:03 PM Lars Povlsen <lars.povlsen@microchip.com> wrote:
>
> With this change a SPI controller can be added without having a IRQ
> associated, and causing all transfers to be polled. For SPI controllers
> without DMA, this can significantly improve performance by less
> interrupt handling overhead.
...
> +#define VALID_IRQ(i) (i >= 0)
drivers/rtc/rtc-cmos.c:95:#define is_valid_irq(n) ((n) > 0)
Candidate to be in include/linux/irq.h ?
...
> + if (VALID_IRQ(dws->irq))
> + free_irq(dws->irq, master);
Isn't free_irq() aware of invalid ones (not found IRQ in the tree or
any other backend container won't do anything)?
> err_free_master:
> spi_controller_put(master);
> return ret;
> --
> 2.26.2
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2020-05-13 15:05 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-13 14:00 [PATCH 00/10] spi: Adding support for Microchip Sparx5 SoC Lars Povlsen
2020-05-13 14:00 ` [PATCH 01/10] spi: dw: Add support for polled operation via no IRQ specified in DT Lars Povlsen
2020-05-13 14:55 ` Andy Shevchenko [this message]
2020-05-19 10:25 ` Lars Povlsen
[not found] ` <20200513142050.GH4803@sirena.org.uk>
2020-05-14 13:04 ` Serge Semin
2020-05-15 9:11 ` Lars Povlsen
[not found] ` <20200513143753.GI4803@sirena.org.uk>
2020-05-19 10:21 ` Lars Povlsen
2020-06-02 19:10 ` Serge Semin
2020-06-09 9:13 ` Lars Povlsen
2020-05-13 14:00 ` [PATCH 02/10] spi: dw: Add support for RX sample delay register Lars Povlsen
2020-06-02 19:39 ` Serge Semin
2020-06-09 10:04 ` Lars Povlsen
2020-05-13 14:00 ` [PATCH 03/10] spi: dw: Add support for client driver memory operations Lars Povlsen
2020-05-13 14:00 ` [PATCH 04/10] dt-bindings: spi: Add bindings for spi-dw-mchp Lars Povlsen
[not found] ` <20200513145213.GJ4803@sirena.org.uk>
2020-05-19 11:47 ` Lars Povlsen
[not found] ` <20200519115829.GI4611@sirena.org.uk>
2020-05-19 12:10 ` Lars Povlsen
2020-06-02 19:49 ` Serge Semin
2020-06-09 10:27 ` Lars Povlsen
2020-05-13 14:00 ` [PATCH 05/10] spi: spi-dw-mmio: Spin off MSCC platforms into spi-dw-mchp Lars Povlsen
[not found] ` <20200513151811.GL4803@sirena.org.uk>
2020-05-19 12:05 ` Lars Povlsen
2020-06-02 21:12 ` Serge Semin
2020-06-10 14:28 ` Lars Povlsen
2020-05-13 14:00 ` [PATCH 06/10] dt-bindings: spi: spi-dw-mchp: Add Sparx5 support Lars Povlsen
2020-06-02 23:07 ` Serge Semin
2020-06-10 12:27 ` Lars Povlsen
2020-05-13 14:00 ` [PATCH 07/10] " Lars Povlsen
[not found] ` <20200514102516.GD5127@sirena.org.uk>
2020-05-19 9:29 ` Lars Povlsen
2020-06-02 23:22 ` Serge Semin
2020-05-13 14:00 ` [PATCH 08/10] arm64: dts: sparx5: Add SPI controller Lars Povlsen
2020-05-13 14:00 ` [PATCH 09/10] arm64: dts: sparx5: Add spi-nor support Lars Povlsen
2020-05-13 14:00 ` [PATCH 10/10] arm64: dts: sparx5: Add spi-nand devices Lars Povlsen
2020-05-29 16:21 ` [PATCH 00/10] spi: Adding support for Microchip Sparx5 SoC Serge Semin
2020-06-02 8:18 ` Lars Povlsen
2020-06-02 8:21 ` Serge Semin
2020-06-02 23:44 ` Serge Semin
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