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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: a589df1d-5465-4c73-5ce4-08d7d6ce1ff1 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Apr 2020 06:21:48.1864 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: LyT59PHHWj6GSLnavDuww2KdiyaGSyPXcixOPVe2Wg/kDs6r6+nMBcX3AaXWNKIsT2XhbI4VXhMWSH23BfUan9y2V2yGalfnSv9s1sHdjbmUSK2MV1CGfcQpJMpGx5IX X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB2684 X-OriginatorOrg: intel.com Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org > -----Original Message----- > From: Rob Herring > Sent: Tuesday, March 31, 2020 12:55 AM > To: Wan Mohamad, Wan Ahmad Zainie > > Cc: broonie@kernel.org; mark.rutland@arm.com; linux-spi@vger.kernel.org; > devicetree@vger.kernel.org > Subject: Re: [PATCH 3/7] dt-bindings: spi: dw-apb-ssi: Convert bindings t= o > json-schema >=20 > On Thu, Mar 12, 2020 at 07:31:25PM +0800, Wan Ahmad Zainie wrote: > > Convert the Synopsis DesignWare dw-apb-ssi binding to DT schema format > > using json-schema. > > > > Suggested-by: Andy Shevchenko > > Signed-off-by: Wan Ahmad Zainie > > > > --- > > .../bindings/spi/snps,dw-apb-ssi.txt | 41 ------- > > .../bindings/spi/snps,dw-apb-ssi.yaml | 102 ++++++++++++++++++ > > 2 files changed, 102 insertions(+), 41 deletions(-) delete mode > > 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt > > create mode 100644 > > Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml > > > > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt > > b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt > > deleted file mode 100644 > > index 3ed08ee9feba..000000000000 > > --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt > > +++ /dev/null > > @@ -1,41 +0,0 @@ > > -Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. > > - > > -Required properties: > > -- compatible : "snps,dw-apb-ssi" or "mscc,-spi", where soc is > > "ocelot" or > > - "jaguar2", or "amazon,alpine-dw-apb-ssi" > > -- reg : The register base for the controller. For "mscc,-spi", a > > second > > - register set is required (named ICPU_CFG:SPI_MST) > > -- interrupts : One interrupt, used by the controller. > > -- #address-cells : <1>, as required by generic SPI binding. > > -- #size-cells : <0>, also as required by generic SPI binding. > > -- clocks : phandles for the clocks, see the description of clock-names > below. > > - The phandle for the "ssi_clk" is required. The phandle for the "pcl= k" clock > > - is optional. If a single clock is specified but no clock-name, it i= s the > > - "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be f= irst. > > - > > -Optional properties: > > -- clock-names : Contains the names of the clocks: > > - "ssi_clk", for the core clock used to generate the external SPI cl= ock. > > - "pclk", the interface clock, required for register access. If a cl= ock domain > > - used to enable this clock then it should be named "pclk_clkdomain= ". > > -- cs-gpios : Specifies the gpio pins to be used for chipselects. > > -- num-cs : The number of chipselects. If omitted, this will default to= 4. > > -- reg-io-width : The I/O register width (in bytes) implemented by > > this > > - device. Supported values are 2 or 4 (the default). > > - > > -Child nodes as per the generic SPI binding. > > - > > -Example: > > - > > - spi@fff00000 { > > - compatible =3D "snps,dw-apb-ssi"; > > - reg =3D <0xfff00000 0x1000>; > > - interrupts =3D <0 154 4>; > > - #address-cells =3D <1>; > > - #size-cells =3D <0>; > > - clocks =3D <&spi_m_clk>; > > - num-cs =3D <2>; > > - cs-gpios =3D <&gpio0 13 0>, > > - <&gpio0 14 0>; > > - }; > > - > > diff --git > > a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml > > b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml > > new file mode 100644 > > index 000000000000..57a789f5d9f3 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml > > @@ -0,0 +1,102 @@ > > +# SPDX-License-Identifier: GPL-2.0-only %YAML 1.2 > > +--- > > +$id: "http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#" > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > > + > > +title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface > > + > > +maintainers: > > + - Mark Brown >=20 > Should be owner for this h/w, not who takes patches. I will ask internally, who is the current owner. >=20 > > + > > +allOf: > > + - $ref: spi-controller.yaml# > > + > > +properties: > > + compatible: > > + oneOf: > > + - items: > > + - enum: > > + - mscc,ocelot-spi > > + - mscc,jaguar2-spi > > + - items: > > + - const: amazon,alpine-dw-apb-ssi > > + - items: > > + - const: snps,dw-apb-ssi >=20 > This can all be a single 'enum'. You only need 'oneOf' if there are a dif= ferent > number of compatible entries. >=20 > > + > > + reg: > > + minItems: 1 > > + maxItems: 2 > > + oneOf: > > + - items: > > + - description: The register base for the controller. > > + - items: > > + - description: The register base for the controller. > > + - description: For "mscc,-spi", a second register set i= s > > + required (named ICPU_CFG:SPI_MST) >=20 > No need for the oneOf. The 2nd case is a superset of the 1st. >=20 > > + > > + interrupts: > > + maxItems: 1 > > + description: One interrupt, used by the controller. >=20 > Can drop description. Not specific to this h/w. >=20 > > + > > + '#address-cells': > > + const: 1 > > + > > + '#size-cells': > > + const: 0 >=20 > Drop these 2. Covered by spi-controller.yaml. >=20 > > + > > + clocks: > > + minItems: 1 > > + maxItems: 2 > > + description: | > > + phandles for the clocks, see the description of clock-names belo= w. > > + The phandle for the "ssi_clk" is required. The phandle for the "= pclk" > > + clock is optional. If a single clock is specified but no clock-n= ame, > > + it is the "ssi_clk" clock. If both clocks are listed, the "ssi_c= lk" > > + must be first. >=20 > Rework like: >=20 > items: > - description: ... > - description: ... >=20 > > + > > + clock-names: > > + items: > > + - const: ssi_clk > > + - const: pclk > > + description: | > > + Contains the names of the clocks. > > + "ssi_clk", for the core clock used to generate the external SPI = clock. > > + "pclk", the interface clock, required for register access. >=20 > No need to repeat what's in clocks. >=20 > > + If a clock domain used to enable this clock then it should be > > + named "pclk_clkdomain". >=20 > Should be a constraint: >=20 > enum: [pclk, pclk_clkdomain] >=20 > But really, it probably should be dropped. I don't understand what the > sentence is supposed to mean. I checked against source code, and no code in drivers/spi/ is using pclk_cl= kdomain, so it is safe to remove.=20 >=20 > > + > > + cs-gpios: > > + description: Specifies the gpio pins to be used for chipselects. >=20 > Can drop, covered by spi-controller.yaml. >=20 > > + > > + num-cs: > > + default: 4 > > + description: The number of chipselects. If omitted, this will defa= ult to 4. >=20 > Constraints? I believe this is not a constraint. Native chip select for this hardware is usually 4. We can have additional c= hip select using GPIOs. >=20 > > + > > + reg-io-width: > > + default: 4 > > + description: | > > + The I/O register width (in bytes) implemented by this device. > > + Supported values are 2 or 4 (the default). >=20 > 2 or 4?, sounds like constraints. Yes, it is either 2 or 4 only. I will fix this and all your comments that I haven't reply above. Thanks for the review and comment. >=20 > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - '#address-cells' > > + - '#size-cells' > > + - clocks > > + > > +examples: > > + - | > > + spi@fff00000 { > > + compatible =3D "snps,dw-apb-ssi"; > > + reg =3D <0xfff00000 0x1000>; > > + interrupts =3D <0 154 4>; > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + clocks =3D <&spi_m_clk>; > > + num-cs =3D <2>; > > + cs-gpios =3D <&gpio0 13 0>, > > + <&gpio0 14 0>; > > + }; > > -- > > 2.17.1 > >