From mboxrd@z Thu Jan 1 00:00:00 1970 From: Subject: Re: [PATCH v2 01/10] spi: atmel-quadspi: cache MR value to avoid a write access Date: Fri, 1 Feb 2019 06:51:39 +0000 Message-ID: References: <20190131161515.21605-1-tudor.ambarus@microchip.com> <20190131161515.21605-2-tudor.ambarus@microchip.com> <20190131175535.3f60ccff@bbrezillon> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Cc: , , , , , , , , , To: Return-path: In-Reply-To: <20190131175535.3f60ccff@bbrezillon> Content-Language: en-US Content-ID: Sender: linux-kernel-owner@vger.kernel.org List-Id: linux-spi.vger.kernel.org DQoNCk9uIDAxLzMxLzIwMTkgMDY6NTUgUE0sIEJvcmlzIEJyZXppbGxvbiB3cm90ZToNCj4gT24g VGh1LCAzMSBKYW4gMjAxOSAxNjoxNToyOCArMDAwMA0KPiA8VHVkb3IuQW1iYXJ1c0BtaWNyb2No aXAuY29tPiB3cm90ZToNCj4gDQo+PiBGcm9tOiBUdWRvciBBbWJhcnVzIDx0dWRvci5hbWJhcnVz QG1pY3JvY2hpcC5jb20+DQo+Pg0KPj4gQ2FjaGUgTVIgdmFsdWUgdG8gYXZvaWQgd3JpdGUgYWNj ZXNzIHdoZW4gc2V0dGluZyB0aGUgY29udHJvbGxlcg0KPj4gaW4gU2VyaWFsIE1lbW9yeSBNb2Rl IChTTU0pLiBTTU0gaXMgc2V0IGluIGV4ZWNfb3AoKSBhbmQgbm90IGF0DQo+PiBwcm9iZSB0aW1l LCB0byBsZXQgcm9vbSBmb3IgZnV0dXJlIHJlZ3VsYXIgU1BJIHN1cHBvcnQuDQo+Pg0KPj4gU2ln bmVkLW9mZi1ieTogVHVkb3IgQW1iYXJ1cyA8dHVkb3IuYW1iYXJ1c0BtaWNyb2NoaXAuY29tPg0K Pj4gLS0tDQo+PiB2MjogY2FjaGUgTVIgdmFsdWUgaW5zdGVhZCBvZiBtb3ZpbmcgdGhlIHdyaXRl IGFjY2VzcyBhdCBwcm9iZQ0KPj4NCj4+ICBkcml2ZXJzL3NwaS9hdG1lbC1xdWFkc3BpLmMgfCA1 ICsrKystDQo+PiAgMSBmaWxlIGNoYW5nZWQsIDQgaW5zZXJ0aW9ucygrKSwgMSBkZWxldGlvbigt KQ0KPj4NCj4+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3NwaS9hdG1lbC1xdWFkc3BpLmMgYi9kcml2 ZXJzL3NwaS9hdG1lbC1xdWFkc3BpLmMNCj4+IGluZGV4IGRkYzcxMjQxMDgxMi4uZmUwNWFlZTVk ODQ1IDEwMDY0NA0KPj4gLS0tIGEvZHJpdmVycy9zcGkvYXRtZWwtcXVhZHNwaS5jDQo+PiArKysg Yi9kcml2ZXJzL3NwaS9hdG1lbC1xdWFkc3BpLmMNCj4+IEBAIC0xNTUsNiArMTU1LDcgQEAgc3Ry dWN0IGF0bWVsX3FzcGkgew0KPj4gIAlzdHJ1Y3QgY2xrCQkqY2xrOw0KPj4gIAlzdHJ1Y3QgcGxh dGZvcm1fZGV2aWNlCSpwZGV2Ow0KPj4gIAl1MzIJCQlwZW5kaW5nOw0KPj4gKwl1MzIJCQltcjsN Cj4+ICAJc3RydWN0IGNvbXBsZXRpb24JY21kX2NvbXBsZXRpb247DQo+PiAgfTsNCj4+ICANCj4+ IEBAIC0yMzgsNyArMjM5LDkgQEAgc3RhdGljIGludCBhdG1lbF9xc3BpX2V4ZWNfb3Aoc3RydWN0 IHNwaV9tZW0gKm1lbSwgY29uc3Qgc3RydWN0IHNwaV9tZW1fb3AgKm9wKQ0KPj4gIAlpY3IgPSBR U1BJX0lDUl9JTlNUKG9wLT5jbWQub3Bjb2RlKTsNCj4+ICAJaWZyID0gUVNQSV9JRlJfSU5TVEVO Ow0KPj4gIA0KPj4gLQlxc3BpX3dyaXRlbChhcSwgUVNQSV9NUiwgUVNQSV9NUl9TTU0pOw0KPj4g KwkvKiBTZXQgdGhlIFFTUEkgY29udHJvbGxlciBpbiBTZXJpYWwgTWVtb3J5IE1vZGUgKi8NCj4+ ICsJaWYgKCEoYXEtPm1yICYgUVNQSV9NUl9TTU0pKQ0KPiANCj4gCWlmIChhcS0+bXIgIT0gUVNQ SV9NUl9TTU0pDQoNCnRoZW4gSSBzaG91bGQgcHJvYmFibHkgcmVuYW1lIG1yIHRvIHNtbS4NCg0K PiANCj4+ICsJCXFzcGlfd3JpdGVsKGFxLCBRU1BJX01SLCBRU1BJX01SX1NNTSk7DQo+IA0KPiBZ b3UgbmVlZCB0byB1cGRhdGUgLT5tciBoZXJlLg0KDQpvZiBjb3Vyc2UsIHRoYW5rcyENCg0KPiAN Cj4+ICANCj4+ICAJbW9kZSA9IGZpbmRfbW9kZShvcCk7DQo+PiAgCWlmIChtb2RlIDwgMCkNCj4g DQo+IA0KPiBfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXw0K PiBsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdA0KPiBsaW51eC1hcm0ta2VybmVsQGxpc3Rz LmluZnJhZGVhZC5vcmcNCj4gaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0 aW5mby9saW51eC1hcm0ta2VybmVsDQo+IA0K