* [PATCH v2 0/2] spi: add BMC support for Intel D5005 card
@ 2021-04-13 22:58 matthew.gerlach
2021-04-13 22:58 ` [PATCH v2 1/2] spi: Add DFL bus driver for Altera SPI Master matthew.gerlach
2021-04-13 22:58 ` [PATCH v2 2/2] hwmon: intel-m10-bmc-hwmon: add sensor support of Intel D5005 card matthew.gerlach
0 siblings, 2 replies; 9+ messages in thread
From: matthew.gerlach @ 2021-04-13 22:58 UTC (permalink / raw)
To: hao.wu, trix, mdf, linux-fpga, linux-kernel, yilun.xu, jdelvare,
linux, lee.jones, linux-hwmon, russell.h.weight, broonie,
linux-spi
Cc: Matthew Gerlach
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
This patch set adds support for the Board Management Controller (BMC)
of an Intel D5005 card. The BMC support requires a Device Feature
List (DFL) bus driver for the Altera SPI Master controller and hwmon
support for the sensors monitored by the BMC.
Patch 1 adds a dfl driver for the Altera SPI Master which is connected
to the board's BMC.
Patch 2 adds hwmon support for the sensors monitored by the board's BMC.
---
v2: move drivers/fpga/dfl-spi-altera.c to drivers/spi/spi-altera-dfl.c
change variable name from m10bmc_bmc_subdevs to m10bmc_d5005_subdevs
added Acked-by: Lee Jones
Matthew Gerlach (2):
spi: Add DFL bus driver for Altera SPI Master
hwmon: intel-m10-bmc-hwmon: add sensor support of Intel D5005 card
drivers/hwmon/intel-m10-bmc-hwmon.c | 122 ++++++++++++++++++++
drivers/mfd/intel-m10-bmc.c | 10 ++
drivers/spi/Kconfig | 9 ++
drivers/spi/Makefile | 1 +
drivers/spi/spi-altera-dfl.c | 221 ++++++++++++++++++++++++++++++++++++
5 files changed, 363 insertions(+)
create mode 100644 drivers/spi/spi-altera-dfl.c
--
1.8.3.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/2] spi: Add DFL bus driver for Altera SPI Master
2021-04-13 22:58 [PATCH v2 0/2] spi: add BMC support for Intel D5005 card matthew.gerlach
@ 2021-04-13 22:58 ` matthew.gerlach
2021-04-14 14:18 ` Mark Brown
2021-04-14 15:29 ` Tom Rix
2021-04-13 22:58 ` [PATCH v2 2/2] hwmon: intel-m10-bmc-hwmon: add sensor support of Intel D5005 card matthew.gerlach
1 sibling, 2 replies; 9+ messages in thread
From: matthew.gerlach @ 2021-04-13 22:58 UTC (permalink / raw)
To: hao.wu, trix, mdf, linux-fpga, linux-kernel, yilun.xu, jdelvare,
linux, lee.jones, linux-hwmon, russell.h.weight, broonie,
linux-spi
Cc: Matthew Gerlach
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
This patch adds a Device Feature List (DFL) bus driver for the
Altera SPI Master controller. The SPI master is connected to an
Intel SPI Slave to Avalon Master Bridge inside an Intel MAX10
BMC Chip.
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
v2: moved drivers/fpga/dfl-spi-altera.c to drivers/spi/spi-altera-dfl.c
---
drivers/spi/Kconfig | 9 ++
drivers/spi/Makefile | 1 +
drivers/spi/spi-altera-dfl.c | 222 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 232 insertions(+)
create mode 100644 drivers/spi/spi-altera-dfl.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 853cf4c..6c6798e 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -63,6 +63,15 @@ config SPI_ALTERA
help
This is the driver for the Altera SPI Controller.
+config SPI_ALTERA_DFL
+ tristate "DFL driver for Altera SPI Controller"
+ depends on FPGA_DFL
+ select SPI_ALTERA
+ help
+ This is a Device Feature List (DFL) bus driver for the
+ Altera SPI master controller. The SPI master is connected
+ to a SPI slave to Avalon Master bridge in a Intel MAX BMC.
+
config SPI_AR934X
tristate "Qualcomm Atheros AR934X/QCA95XX SPI controller driver"
depends on ATH79 || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 29fee71..2e348ea 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
# SPI master controller drivers (bus)
obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
+obj-$(CONFIG_SPI_ALTERA_DFL) += spi-altera-dfl.o
obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o
obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o
obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
diff --git a/drivers/spi/spi-altera-dfl.c b/drivers/spi/spi-altera-dfl.c
new file mode 100644
index 0000000..8ddfc5d
--- /dev/null
+++ b/drivers/spi/spi-altera-dfl.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DFL bus driver for Altera SPI Master
+ *
+ * Copyright (C) 2020 Intel Corporation, Inc.
+ *
+ * Authors:
+ * Matthew Gerlach <matthew.gerlach@linux.intel.com>
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/stddef.h>
+#include <linux/errno.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/bitfield.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/regmap.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/altera.h>
+#include <linux/dfl.h>
+
+struct dfl_altera_spi {
+ void __iomem *base;
+ struct regmap *regmap;
+ struct device *dev;
+ struct platform_device *altr_spi;
+};
+
+#define SPI_CORE_PARAMETER 0x8
+#define SHIFT_MODE BIT_ULL(1)
+#define SHIFT_MODE_MSB 0
+#define SHIFT_MODE_LSB 1
+#define DATA_WIDTH GENMASK_ULL(7, 2)
+#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
+#define CLK_POLARITY BIT_ULL(14)
+#define CLK_PHASE BIT_ULL(15)
+#define PERIPHERAL_ID GENMASK_ULL(47, 32)
+#define SPI_CLK GENMASK_ULL(31, 22)
+#define SPI_INDIRECT_ACC_OFST 0x10
+
+#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
+#define INDIRECT_WR BIT_ULL(8)
+#define INDIRECT_RD BIT_ULL(9)
+#define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8)
+#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
+#define INDIRECT_DEBUG BIT_ULL(32)
+#define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10)
+#define INDIRECT_TIMEOUT 10000
+
+static int indirect_bus_reg_read(void *context, unsigned int reg,
+ unsigned int *val)
+{
+ struct dfl_altera_spi *aspi = context;
+ void __iomem *base = aspi->base;
+ int loops;
+ u64 v;
+
+ writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
+
+ loops = 0;
+ while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
+ (loops++ < INDIRECT_TIMEOUT))
+ cpu_relax();
+
+ if (loops >= INDIRECT_TIMEOUT) {
+ pr_err("%s timed out %d\n", __func__, loops);
+ return -ETIME;
+ }
+
+ v = readq(base + INDIRECT_RD_DATA);
+
+ *val = v & INDIRECT_DATA_MASK;
+
+ return 0;
+}
+
+static int indirect_bus_reg_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ struct dfl_altera_spi *aspi = context;
+ void __iomem *base = aspi->base;
+ int loops;
+
+ writeq(val, base + INDIRECT_WR_DATA);
+ writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
+
+ loops = 0;
+ while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
+ (loops++ < INDIRECT_TIMEOUT))
+ cpu_relax();
+
+ if (loops >= INDIRECT_TIMEOUT) {
+ pr_err("%s timed out %d\n", __func__, loops);
+ return -ETIME;
+ }
+ return 0;
+}
+
+static const struct regmap_config indirect_regbus_cfg = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .fast_io = true,
+ .max_register = 24,
+
+ .reg_write = indirect_bus_reg_write,
+ .reg_read = indirect_bus_reg_read,
+};
+
+static struct spi_board_info m10_bmc_info = {
+ .modalias = "m10-d5005",
+ .max_speed_hz = 12500000,
+ .bus_num = 0,
+ .chip_select = 0,
+};
+
+static struct platform_device *create_cntrl(struct device *dev,
+ void __iomem *base,
+ struct spi_board_info *m10_info)
+{
+ struct altera_spi_platform_data pdata;
+ struct platform_device_info pdevinfo;
+ u64 v;
+
+ v = readq(base + SPI_CORE_PARAMETER);
+
+ memset(&pdata, 0, sizeof(pdata));
+ pdata.mode_bits = SPI_CS_HIGH;
+ if (FIELD_GET(CLK_POLARITY, v))
+ pdata.mode_bits |= SPI_CPOL;
+ if (FIELD_GET(CLK_PHASE, v))
+ pdata.mode_bits |= SPI_CPHA;
+
+ pdata.num_chipselect = FIELD_GET(NUM_CHIPSELECT, v);
+ pdata.bits_per_word_mask =
+ SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v));
+
+ pdata.num_devices = 1;
+ pdata.devices = m10_info;
+
+ dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__,
+ pdata.num_chipselect, pdata.bits_per_word_mask,
+ pdata.mode_bits);
+
+ memset(&pdevinfo, 0, sizeof(pdevinfo));
+
+ pdevinfo.name = "subdev_spi_altera";
+ pdevinfo.id = PLATFORM_DEVID_AUTO;
+ pdevinfo.parent = dev;
+ pdevinfo.data = &pdata;
+ pdevinfo.size_data = sizeof(pdata);
+
+ return platform_device_register_full(&pdevinfo);
+}
+static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
+{
+ struct device *dev = &dfl_dev->dev;
+ struct dfl_altera_spi *aspi;
+
+ aspi = devm_kzalloc(dev, sizeof(*aspi), GFP_KERNEL);
+
+ if (!aspi)
+ return -ENOMEM;
+
+ dev_set_drvdata(dev, aspi);
+
+ aspi->dev = dev;
+
+ aspi->base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
+
+ if (IS_ERR(aspi->base)) {
+ dev_err(dev, "%s get mem resource fail!\n", __func__);
+ return PTR_ERR(aspi->base);
+ }
+
+ aspi->regmap = devm_regmap_init(dev, NULL, aspi, &indirect_regbus_cfg);
+ if (IS_ERR(aspi->regmap))
+ return PTR_ERR(aspi->regmap);
+
+ aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_bmc_info);
+
+ if (IS_ERR(aspi->altr_spi)) {
+ dev_err(dev, "%s failed to create spi platform driver\n",
+ __func__);
+ return PTR_ERR(aspi->base);
+ }
+
+ return 0;
+}
+
+static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
+{
+ struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
+
+ platform_device_unregister(aspi->altr_spi);
+}
+
+#define FME_FEATURE_ID_MAX10_SPI 0xe
+
+static const struct dfl_device_id dfl_spi_altera_ids[] = {
+ { FME_ID, FME_FEATURE_ID_MAX10_SPI },
+ { }
+};
+
+static struct dfl_driver dfl_spi_altera_driver = {
+ .drv = {
+ .name = "dfl-spi-altera",
+ },
+ .id_table = dfl_spi_altera_ids,
+ .probe = dfl_spi_altera_probe,
+ .remove = dfl_spi_altera_remove,
+};
+
+module_dfl_driver(dfl_spi_altera_driver);
+
+MODULE_DEVICE_TABLE(dfl, dfl_spi_altera_ids);
+MODULE_DESCRIPTION("DFL spi altera driver");
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL v2");
--
1.8.3.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 2/2] hwmon: intel-m10-bmc-hwmon: add sensor support of Intel D5005 card
2021-04-13 22:58 [PATCH v2 0/2] spi: add BMC support for Intel D5005 card matthew.gerlach
2021-04-13 22:58 ` [PATCH v2 1/2] spi: Add DFL bus driver for Altera SPI Master matthew.gerlach
@ 2021-04-13 22:58 ` matthew.gerlach
2021-04-13 23:11 ` Guenter Roeck
2021-04-14 15:36 ` Tom Rix
1 sibling, 2 replies; 9+ messages in thread
From: matthew.gerlach @ 2021-04-13 22:58 UTC (permalink / raw)
To: hao.wu, trix, mdf, linux-fpga, linux-kernel, yilun.xu, jdelvare,
linux, lee.jones, linux-hwmon, russell.h.weight, broonie,
linux-spi
Cc: Matthew Gerlach, Russ Weight
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Like the Intel N3000 card, the Intel D5005 has a MAX10 based
BMC. This commit adds support for the D5005 sensors that are
monitored by the MAX10 BMC.
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Russ Weight <russell.h.weight@linux.intel.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
---
v2: change variable name from m10bmc_bmc_subdevs to m10bmc_d5005_subdevs
added Acked-by: Lee Jones
---
drivers/hwmon/intel-m10-bmc-hwmon.c | 122 ++++++++++++++++++++++++++++++++++++
drivers/mfd/intel-m10-bmc.c | 10 +++
2 files changed, 132 insertions(+)
diff --git a/drivers/hwmon/intel-m10-bmc-hwmon.c b/drivers/hwmon/intel-m10-bmc-hwmon.c
index 17d5e6b..bd7ed2e 100644
--- a/drivers/hwmon/intel-m10-bmc-hwmon.c
+++ b/drivers/hwmon/intel-m10-bmc-hwmon.c
@@ -99,6 +99,50 @@ struct m10bmc_hwmon {
NULL
};
+static const struct m10bmc_sdata d5005bmc_temp_tbl[] = {
+ { 0x100, 0x104, 0x108, 0x10c, 0x0, 500, "Board Inlet Air Temperature" },
+ { 0x110, 0x114, 0x118, 0x0, 0x0, 500, "FPGA Core Temperature" },
+ { 0x11c, 0x120, 0x124, 0x128, 0x0, 500, "Board Exhaust Air Temperature" },
+ { 0x12c, 0x130, 0x134, 0x0, 0x0, 500, "FPGA Transceiver Temperature" },
+ { 0x138, 0x13c, 0x140, 0x144, 0x0, 500, "RDIMM0 Temperature" },
+ { 0x148, 0x14c, 0x150, 0x154, 0x0, 500, "RDIMM1 Temperature" },
+ { 0x158, 0x15c, 0x160, 0x164, 0x0, 500, "RDIMM2 Temperature" },
+ { 0x168, 0x16c, 0x170, 0x174, 0x0, 500, "RDIMM3 Temperature" },
+ { 0x178, 0x17c, 0x180, 0x0, 0x0, 500, "QSFP0 Temperature" },
+ { 0x188, 0x18c, 0x190, 0x0, 0x0, 500, "QSFP1 Temperature" },
+ { 0x1a0, 0x1a4, 0x1a8, 0x0, 0x0, 500, "3.3v Temperature" },
+ { 0x1bc, 0x1c0, 0x1c4, 0x0, 0x0, 500, "VCCERAM Temperature" },
+ { 0x1d8, 0x1dc, 0x1e0, 0x0, 0x0, 500, "VCCR Temperature" },
+ { 0x1f4, 0x1f8, 0x1fc, 0x0, 0x0, 500, "VCCT Temperature" },
+ { 0x210, 0x214, 0x218, 0x0, 0x0, 500, "1.8v Temperature" },
+ { 0x22c, 0x230, 0x234, 0x0, 0x0, 500, "12v Backplane Temperature" },
+ { 0x248, 0x24c, 0x250, 0x0, 0x0, 500, "12v AUX Temperature" },
+};
+
+static const struct m10bmc_sdata d5005bmc_in_tbl[] = {
+ { 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QSFP0 Supply Voltage" },
+ { 0x194, 0x0, 0x0, 0x0, 0x0, 1, "QSFP1 Supply Voltage" },
+ { 0x198, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage" },
+ { 0x1ac, 0x1b0, 0x1b4, 0x0, 0x0, 1, "3.3v Voltage" },
+ { 0x1c8, 0x1cc, 0x1d0, 0x0, 0x0, 1, "VCCERAM Voltage" },
+ { 0x1e4, 0x1e8, 0x1ec, 0x0, 0x0, 1, "VCCR Voltage" },
+ { 0x200, 0x204, 0x208, 0x0, 0x0, 1, "VCCT Voltage" },
+ { 0x21c, 0x220, 0x224, 0x0, 0x0, 1, "1.8v Voltage" },
+ { 0x238, 0x0, 0x0, 0x0, 0x23c, 1, "12v Backplane Voltage" },
+ { 0x254, 0x0, 0x0, 0x0, 0x258, 1, "12v AUX Voltage" },
+};
+
+static const struct m10bmc_sdata d5005bmc_curr_tbl[] = {
+ { 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Current" },
+ { 0x1b8, 0x0, 0x0, 0x0, 0x0, 1, "3.3v Current" },
+ { 0x1d4, 0x0, 0x0, 0x0, 0x0, 1, "VCCERAM Current" },
+ { 0x1f0, 0x0, 0x0, 0x0, 0x0, 1, "VCCR Current" },
+ { 0x20c, 0x0, 0x0, 0x0, 0x0, 1, "VCCT Current" },
+ { 0x228, 0x0, 0x0, 0x0, 0x0, 1, "1.8v Current" },
+ { 0x240, 0x244, 0x0, 0x0, 0x0, 1, "12v Backplane Current" },
+ { 0x25c, 0x260, 0x0, 0x0, 0x0, 1, "12v AUX Current" },
+};
+
static const struct m10bmc_hwmon_board_data n3000bmc_hwmon_bdata = {
.tables = {
[hwmon_temp] = n3000bmc_temp_tbl,
@@ -110,6 +154,80 @@ struct m10bmc_hwmon {
.hinfo = n3000bmc_hinfo,
};
+static const struct hwmon_channel_info *d5005bmc_hinfo[] = {
+ HWMON_CHANNEL_INFO(temp,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
+ HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
+ HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
+ HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
+ HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
+ HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
+ HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
+ HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
+ HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
+ HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
+ HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
+ HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
+ HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
+ HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
+ HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
+ HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
+ HWMON_T_LABEL,
+ HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
+ HWMON_T_LABEL),
+ HWMON_CHANNEL_INFO(in,
+ HWMON_I_INPUT | HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
+ HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
+ HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
+ HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
+ HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
+ HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_LABEL,
+ HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_LABEL),
+ HWMON_CHANNEL_INFO(curr,
+ HWMON_C_INPUT | HWMON_C_LABEL,
+ HWMON_C_INPUT | HWMON_C_LABEL,
+ HWMON_C_INPUT | HWMON_C_LABEL,
+ HWMON_C_INPUT | HWMON_C_LABEL,
+ HWMON_C_INPUT | HWMON_C_LABEL,
+ HWMON_C_INPUT | HWMON_C_LABEL,
+ HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_LABEL,
+ HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_LABEL),
+ NULL
+};
+
+static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = {
+ .tables = {
+ [hwmon_temp] = d5005bmc_temp_tbl,
+ [hwmon_in] = d5005bmc_in_tbl,
+ [hwmon_curr] = d5005bmc_curr_tbl,
+ },
+
+ .hinfo = d5005bmc_hinfo,
+};
+
static umode_t
m10bmc_hwmon_is_visible(const void *data, enum hwmon_sensor_types type,
u32 attr, int channel)
@@ -316,6 +434,10 @@ static int m10bmc_hwmon_probe(struct platform_device *pdev)
.name = "n3000bmc-hwmon",
.driver_data = (unsigned long)&n3000bmc_hwmon_bdata,
},
+ {
+ .name = "d5005bmc-hwmon",
+ .driver_data = (unsigned long)&d5005bmc_hwmon_bdata,
+ },
{ }
};
diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c
index 1161933..1a9bfb7 100644
--- a/drivers/mfd/intel-m10-bmc.c
+++ b/drivers/mfd/intel-m10-bmc.c
@@ -15,6 +15,11 @@
enum m10bmc_type {
M10_N3000,
+ M10_D5005
+};
+
+static struct mfd_cell m10bmc_d5005_subdevs[] = {
+ { .name = "d5005bmc-hwmon" },
};
static struct mfd_cell m10bmc_pacn3000_subdevs[] = {
@@ -183,6 +188,10 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
cells = m10bmc_pacn3000_subdevs;
n_cell = ARRAY_SIZE(m10bmc_pacn3000_subdevs);
break;
+ case M10_D5005:
+ cells = m10bmc_d5005_subdevs;
+ n_cell = ARRAY_SIZE(m10bmc_d5005_subdevs);
+ break;
default:
return -ENODEV;
}
@@ -197,6 +206,7 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
static const struct spi_device_id m10bmc_spi_id[] = {
{ "m10-n3000", M10_N3000 },
+ { "m10-d5005", M10_D5005 },
{ }
};
MODULE_DEVICE_TABLE(spi, m10bmc_spi_id);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/2] hwmon: intel-m10-bmc-hwmon: add sensor support of Intel D5005 card
2021-04-13 22:58 ` [PATCH v2 2/2] hwmon: intel-m10-bmc-hwmon: add sensor support of Intel D5005 card matthew.gerlach
@ 2021-04-13 23:11 ` Guenter Roeck
2021-04-14 15:36 ` Tom Rix
1 sibling, 0 replies; 9+ messages in thread
From: Guenter Roeck @ 2021-04-13 23:11 UTC (permalink / raw)
To: matthew.gerlach
Cc: hao.wu, trix, mdf, linux-fpga, linux-kernel, yilun.xu, jdelvare,
lee.jones, linux-hwmon, russell.h.weight, broonie, linux-spi,
Russ Weight
On Tue, Apr 13, 2021 at 03:58:35PM -0700, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>
> Like the Intel N3000 card, the Intel D5005 has a MAX10 based
> BMC. This commit adds support for the D5005 sensors that are
> monitored by the MAX10 BMC.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Signed-off-by: Russ Weight <russell.h.weight@linux.intel.com>
> Acked-by: Lee Jones <lee.jones@linaro.org>
Applied to hwmon-next.
Thanks,
Guenter
> ---
> v2: change variable name from m10bmc_bmc_subdevs to m10bmc_d5005_subdevs
> added Acked-by: Lee Jones
> ---
> drivers/hwmon/intel-m10-bmc-hwmon.c | 122 ++++++++++++++++++++++++++++++++++++
> drivers/mfd/intel-m10-bmc.c | 10 +++
> 2 files changed, 132 insertions(+)
>
> diff --git a/drivers/hwmon/intel-m10-bmc-hwmon.c b/drivers/hwmon/intel-m10-bmc-hwmon.c
> index 17d5e6b..bd7ed2e 100644
> --- a/drivers/hwmon/intel-m10-bmc-hwmon.c
> +++ b/drivers/hwmon/intel-m10-bmc-hwmon.c
> @@ -99,6 +99,50 @@ struct m10bmc_hwmon {
> NULL
> };
>
> +static const struct m10bmc_sdata d5005bmc_temp_tbl[] = {
> + { 0x100, 0x104, 0x108, 0x10c, 0x0, 500, "Board Inlet Air Temperature" },
> + { 0x110, 0x114, 0x118, 0x0, 0x0, 500, "FPGA Core Temperature" },
> + { 0x11c, 0x120, 0x124, 0x128, 0x0, 500, "Board Exhaust Air Temperature" },
> + { 0x12c, 0x130, 0x134, 0x0, 0x0, 500, "FPGA Transceiver Temperature" },
> + { 0x138, 0x13c, 0x140, 0x144, 0x0, 500, "RDIMM0 Temperature" },
> + { 0x148, 0x14c, 0x150, 0x154, 0x0, 500, "RDIMM1 Temperature" },
> + { 0x158, 0x15c, 0x160, 0x164, 0x0, 500, "RDIMM2 Temperature" },
> + { 0x168, 0x16c, 0x170, 0x174, 0x0, 500, "RDIMM3 Temperature" },
> + { 0x178, 0x17c, 0x180, 0x0, 0x0, 500, "QSFP0 Temperature" },
> + { 0x188, 0x18c, 0x190, 0x0, 0x0, 500, "QSFP1 Temperature" },
> + { 0x1a0, 0x1a4, 0x1a8, 0x0, 0x0, 500, "3.3v Temperature" },
> + { 0x1bc, 0x1c0, 0x1c4, 0x0, 0x0, 500, "VCCERAM Temperature" },
> + { 0x1d8, 0x1dc, 0x1e0, 0x0, 0x0, 500, "VCCR Temperature" },
> + { 0x1f4, 0x1f8, 0x1fc, 0x0, 0x0, 500, "VCCT Temperature" },
> + { 0x210, 0x214, 0x218, 0x0, 0x0, 500, "1.8v Temperature" },
> + { 0x22c, 0x230, 0x234, 0x0, 0x0, 500, "12v Backplane Temperature" },
> + { 0x248, 0x24c, 0x250, 0x0, 0x0, 500, "12v AUX Temperature" },
> +};
> +
> +static const struct m10bmc_sdata d5005bmc_in_tbl[] = {
> + { 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QSFP0 Supply Voltage" },
> + { 0x194, 0x0, 0x0, 0x0, 0x0, 1, "QSFP1 Supply Voltage" },
> + { 0x198, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage" },
> + { 0x1ac, 0x1b0, 0x1b4, 0x0, 0x0, 1, "3.3v Voltage" },
> + { 0x1c8, 0x1cc, 0x1d0, 0x0, 0x0, 1, "VCCERAM Voltage" },
> + { 0x1e4, 0x1e8, 0x1ec, 0x0, 0x0, 1, "VCCR Voltage" },
> + { 0x200, 0x204, 0x208, 0x0, 0x0, 1, "VCCT Voltage" },
> + { 0x21c, 0x220, 0x224, 0x0, 0x0, 1, "1.8v Voltage" },
> + { 0x238, 0x0, 0x0, 0x0, 0x23c, 1, "12v Backplane Voltage" },
> + { 0x254, 0x0, 0x0, 0x0, 0x258, 1, "12v AUX Voltage" },
> +};
> +
> +static const struct m10bmc_sdata d5005bmc_curr_tbl[] = {
> + { 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Current" },
> + { 0x1b8, 0x0, 0x0, 0x0, 0x0, 1, "3.3v Current" },
> + { 0x1d4, 0x0, 0x0, 0x0, 0x0, 1, "VCCERAM Current" },
> + { 0x1f0, 0x0, 0x0, 0x0, 0x0, 1, "VCCR Current" },
> + { 0x20c, 0x0, 0x0, 0x0, 0x0, 1, "VCCT Current" },
> + { 0x228, 0x0, 0x0, 0x0, 0x0, 1, "1.8v Current" },
> + { 0x240, 0x244, 0x0, 0x0, 0x0, 1, "12v Backplane Current" },
> + { 0x25c, 0x260, 0x0, 0x0, 0x0, 1, "12v AUX Current" },
> +};
> +
> static const struct m10bmc_hwmon_board_data n3000bmc_hwmon_bdata = {
> .tables = {
> [hwmon_temp] = n3000bmc_temp_tbl,
> @@ -110,6 +154,80 @@ struct m10bmc_hwmon {
> .hinfo = n3000bmc_hinfo,
> };
>
> +static const struct hwmon_channel_info *d5005bmc_hinfo[] = {
> + HWMON_CHANNEL_INFO(temp,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
> + HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
> + HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
> + HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
> + HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
> + HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
> + HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL),
> + HWMON_CHANNEL_INFO(in,
> + HWMON_I_INPUT | HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
> + HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
> + HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
> + HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
> + HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
> + HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_LABEL),
> + HWMON_CHANNEL_INFO(curr,
> + HWMON_C_INPUT | HWMON_C_LABEL,
> + HWMON_C_INPUT | HWMON_C_LABEL,
> + HWMON_C_INPUT | HWMON_C_LABEL,
> + HWMON_C_INPUT | HWMON_C_LABEL,
> + HWMON_C_INPUT | HWMON_C_LABEL,
> + HWMON_C_INPUT | HWMON_C_LABEL,
> + HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_LABEL,
> + HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_LABEL),
> + NULL
> +};
> +
> +static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = {
> + .tables = {
> + [hwmon_temp] = d5005bmc_temp_tbl,
> + [hwmon_in] = d5005bmc_in_tbl,
> + [hwmon_curr] = d5005bmc_curr_tbl,
> + },
> +
> + .hinfo = d5005bmc_hinfo,
> +};
> +
> static umode_t
> m10bmc_hwmon_is_visible(const void *data, enum hwmon_sensor_types type,
> u32 attr, int channel)
> @@ -316,6 +434,10 @@ static int m10bmc_hwmon_probe(struct platform_device *pdev)
> .name = "n3000bmc-hwmon",
> .driver_data = (unsigned long)&n3000bmc_hwmon_bdata,
> },
> + {
> + .name = "d5005bmc-hwmon",
> + .driver_data = (unsigned long)&d5005bmc_hwmon_bdata,
> + },
> { }
> };
>
> diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c
> index 1161933..1a9bfb7 100644
> --- a/drivers/mfd/intel-m10-bmc.c
> +++ b/drivers/mfd/intel-m10-bmc.c
> @@ -15,6 +15,11 @@
>
> enum m10bmc_type {
> M10_N3000,
> + M10_D5005
> +};
> +
> +static struct mfd_cell m10bmc_d5005_subdevs[] = {
> + { .name = "d5005bmc-hwmon" },
> };
>
> static struct mfd_cell m10bmc_pacn3000_subdevs[] = {
> @@ -183,6 +188,10 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
> cells = m10bmc_pacn3000_subdevs;
> n_cell = ARRAY_SIZE(m10bmc_pacn3000_subdevs);
> break;
> + case M10_D5005:
> + cells = m10bmc_d5005_subdevs;
> + n_cell = ARRAY_SIZE(m10bmc_d5005_subdevs);
> + break;
> default:
> return -ENODEV;
> }
> @@ -197,6 +206,7 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
>
> static const struct spi_device_id m10bmc_spi_id[] = {
> { "m10-n3000", M10_N3000 },
> + { "m10-d5005", M10_D5005 },
> { }
> };
> MODULE_DEVICE_TABLE(spi, m10bmc_spi_id);
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] spi: Add DFL bus driver for Altera SPI Master
2021-04-13 22:58 ` [PATCH v2 1/2] spi: Add DFL bus driver for Altera SPI Master matthew.gerlach
@ 2021-04-14 14:18 ` Mark Brown
2021-04-14 19:09 ` matthew.gerlach
2021-04-14 15:29 ` Tom Rix
1 sibling, 1 reply; 9+ messages in thread
From: Mark Brown @ 2021-04-14 14:18 UTC (permalink / raw)
To: matthew.gerlach
Cc: hao.wu, trix, mdf, linux-fpga, linux-kernel, yilun.xu, jdelvare,
linux, lee.jones, linux-hwmon, russell.h.weight, linux-spi
[-- Attachment #1: Type: text/plain, Size: 702 bytes --]
On Tue, Apr 13, 2021 at 03:58:34PM -0700, matthew.gerlach@linux.intel.com wrote:
> +++ b/drivers/spi/spi-altera-dfl.c
> @@ -0,0 +1,222 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * DFL bus driver for Altera SPI Master
> + *
Please make the entire comment a C++ one so things look more
intentional.
> + memset(&pdevinfo, 0, sizeof(pdevinfo));
> +
> + pdevinfo.name = "subdev_spi_altera";
> + pdevinfo.id = PLATFORM_DEVID_AUTO;
> + pdevinfo.parent = dev;
> + pdevinfo.data = &pdata;
> + pdevinfo.size_data = sizeof(pdata);
> +
> + return platform_device_register_full(&pdevinfo);
Don't create a platform device here, extend the spi-altera driver to
register with both DFL and platform buses.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] spi: Add DFL bus driver for Altera SPI Master
2021-04-13 22:58 ` [PATCH v2 1/2] spi: Add DFL bus driver for Altera SPI Master matthew.gerlach
2021-04-14 14:18 ` Mark Brown
@ 2021-04-14 15:29 ` Tom Rix
1 sibling, 0 replies; 9+ messages in thread
From: Tom Rix @ 2021-04-14 15:29 UTC (permalink / raw)
To: matthew.gerlach, hao.wu, mdf, linux-fpga, linux-kernel, yilun.xu,
jdelvare, linux, lee.jones, linux-hwmon, russell.h.weight,
broonie, linux-spi
On 4/13/21 3:58 PM, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>
> This patch adds a Device Feature List (DFL) bus driver for the
> Altera SPI Master controller. The SPI master is connected to an
> Intel SPI Slave to Avalon Master Bridge inside an Intel MAX10
> BMC Chip.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> ---
> v2: moved drivers/fpga/dfl-spi-altera.c to drivers/spi/spi-altera-dfl.c
> ---
> drivers/spi/Kconfig | 9 ++
> drivers/spi/Makefile | 1 +
> drivers/spi/spi-altera-dfl.c | 222 +++++++++++++++++++++++++++++++++++++++++++
does this need a MAINTAINER's entry ?
> 3 files changed, 232 insertions(+)
> create mode 100644 drivers/spi/spi-altera-dfl.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 853cf4c..6c6798e 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -63,6 +63,15 @@ config SPI_ALTERA
> help
> This is the driver for the Altera SPI Controller.
>
> +config SPI_ALTERA_DFL
> + tristate "DFL driver for Altera SPI Controller"
> + depends on FPGA_DFL
> + select SPI_ALTERA
> + help
> + This is a Device Feature List (DFL) bus driver for the
> + Altera SPI master controller. The SPI master is connected
> + to a SPI slave to Avalon Master bridge in a Intel MAX BMC.
Last sentence is a little confusing with two 'masters', could this be
The SPI master is connected to the Avalon SPI bridge in the Intel Max10 BMC.
?
> +
> config SPI_AR934X
> tristate "Qualcomm Atheros AR934X/QCA95XX SPI controller driver"
> depends on ATH79 || COMPILE_TEST
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 29fee71..2e348ea 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -15,6 +15,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
>
> # SPI master controller drivers (bus)
> obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
> +obj-$(CONFIG_SPI_ALTERA_DFL) += spi-altera-dfl.o
> obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o
> obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o
> obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
> diff --git a/drivers/spi/spi-altera-dfl.c b/drivers/spi/spi-altera-dfl.c
> new file mode 100644
> index 0000000..8ddfc5d
> --- /dev/null
> +++ b/drivers/spi/spi-altera-dfl.c
> @@ -0,0 +1,222 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * DFL bus driver for Altera SPI Master
> + *
> + * Copyright (C) 2020 Intel Corporation, Inc.
> + *
> + * Authors:
> + * Matthew Gerlach <matthew.gerlach@linux.intel.com>
> + */
> +
> +#include <linux/types.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/stddef.h>
> +#include <linux/errno.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include <linux/bitfield.h>
> +#include <linux/io-64-nonatomic-lo-hi.h>
> +#include <linux/regmap.h>
> +#include <linux/spi/spi.h>
> +#include <linux/spi/altera.h>
> +#include <linux/dfl.h>
> +
> +struct dfl_altera_spi {
> + void __iomem *base;
> + struct regmap *regmap;
> + struct device *dev;
> + struct platform_device *altr_spi;
the read/write can take a while, is a lock needed ?
> +};
> +
> +#define SPI_CORE_PARAMETER 0x8
a prefix would like 'DFL_' would make this less likely to have namespace
issues.
> +#define SHIFT_MODE BIT_ULL(1)
> +#define SHIFT_MODE_MSB 0
> +#define SHIFT_MODE_LSB 1
> +#define DATA_WIDTH GENMASK_ULL(7, 2)
> +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> +#define CLK_POLARITY BIT_ULL(14)
> +#define CLK_PHASE BIT_ULL(15)
> +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> +#define SPI_CLK GENMASK_ULL(31, 22)
> +#define SPI_INDIRECT_ACC_OFST 0x10
> +
> +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
checkpatch --strict complains here and similar, preferring spaces around
the '+'
> +#define INDIRECT_WR BIT_ULL(8)
> +#define INDIRECT_RD BIT_ULL(9)
> +#define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8)
> +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> +#define INDIRECT_DEBUG BIT_ULL(32)
> +#define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10)
> +#define INDIRECT_TIMEOUT 10000
this does not have units of time, maybe rename to INDIRECT_RETRY_COUNT
> +
> +static int indirect_bus_reg_read(void *context, unsigned int reg,
> + unsigned int *val)
> +{
> + struct dfl_altera_spi *aspi = context;
> + void __iomem *base = aspi->base;
> + int loops;
could initialize loop here
> + u64 v;
> +
> + writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
is input 'reg' checked elsewhere ?
> +
> + loops = 0;
> + while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
> + (loops++ < INDIRECT_TIMEOUT))
> + cpu_relax();
> +
> + if (loops >= INDIRECT_TIMEOUT) {
> + pr_err("%s timed out %d\n", __func__, loops);
> + return -ETIME;
maybe -EBUSY ?
> + }
> +
> + v = readq(base + INDIRECT_RD_DATA);
> +
> + *val = v & INDIRECT_DATA_MASK;
> +
> + return 0;
> +}
> +
> +static int indirect_bus_reg_write(void *context, unsigned int reg,
> + unsigned int val)
> +{
> + struct dfl_altera_spi *aspi = context;
> + void __iomem *base = aspi->base;
> + int loops;
> +
> + writeq(val, base + INDIRECT_WR_DATA);
> + writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
> +
> + loops = 0;
> + while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
> + (loops++ < INDIRECT_TIMEOUT))
> + cpu_relax();
> +
> + if (loops >= INDIRECT_TIMEOUT) {
> + pr_err("%s timed out %d\n", __func__, loops);
> + return -ETIME;
> + }
> + return 0;
> +}
> +
> +static const struct regmap_config indirect_regbus_cfg = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .fast_io = true,
> + .max_register = 24,
> +
> + .reg_write = indirect_bus_reg_write,
> + .reg_read = indirect_bus_reg_read,
> +};
> +
> +static struct spi_board_info m10_bmc_info = {
> + .modalias = "m10-d5005",
> + .max_speed_hz = 12500000,
> + .bus_num = 0,
> + .chip_select = 0,
> +};
> +
> +static struct platform_device *create_cntrl(struct device *dev,
> + void __iomem *base,
> + struct spi_board_info *m10_info)
> +{
could this function be inlined to probe ?
> + struct altera_spi_platform_data pdata;
> + struct platform_device_info pdevinfo;
> + u64 v;
> +
> + v = readq(base + SPI_CORE_PARAMETER);
move down two lines to before the if-checks that use it
> +
> + memset(&pdata, 0, sizeof(pdata));
> + pdata.mode_bits = SPI_CS_HIGH;
> + if (FIELD_GET(CLK_POLARITY, v))
> + pdata.mode_bits |= SPI_CPOL;
> + if (FIELD_GET(CLK_PHASE, v))
> + pdata.mode_bits |= SPI_CPHA;
> +
> + pdata.num_chipselect = FIELD_GET(NUM_CHIPSELECT, v);
> + pdata.bits_per_word_mask =
> + SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v));
> +
> + pdata.num_devices = 1;
> + pdata.devices = m10_info;
> +
> + dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__,
> + pdata.num_chipselect, pdata.bits_per_word_mask,
> + pdata.mode_bits);
> +
> + memset(&pdevinfo, 0, sizeof(pdevinfo));
> +
> + pdevinfo.name = "subdev_spi_altera";
> + pdevinfo.id = PLATFORM_DEVID_AUTO;
> + pdevinfo.parent = dev;
> + pdevinfo.data = &pdata;
> + pdevinfo.size_data = sizeof(pdata);
> +
> + return platform_device_register_full(&pdevinfo);
> +}
> +static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
> +{
> + struct device *dev = &dfl_dev->dev;
> + struct dfl_altera_spi *aspi;
> +
> + aspi = devm_kzalloc(dev, sizeof(*aspi), GFP_KERNEL);
> +
> + if (!aspi)
> + return -ENOMEM;
> +
> + dev_set_drvdata(dev, aspi);
> +
> + aspi->dev = dev;
> +
> + aspi->base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
> +
> + if (IS_ERR(aspi->base)) {
> + dev_err(dev, "%s get mem resource fail!\n", __func__);
> + return PTR_ERR(aspi->base);
> + }
> +
> + aspi->regmap = devm_regmap_init(dev, NULL, aspi, &indirect_regbus_cfg);
> + if (IS_ERR(aspi->regmap))
> + return PTR_ERR(aspi->regmap);
> +
> + aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_bmc_info);
it does not seem like this can fail for device reasons. is there a
sanity check on the reg values that could be done ?
Tom
> +
> + if (IS_ERR(aspi->altr_spi)) {
> + dev_err(dev, "%s failed to create spi platform driver\n",
> + __func__);
> + return PTR_ERR(aspi->base);
> + }
> +
> + return 0;
> +}
> +
> +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> +{
> + struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> +
> + platform_device_unregister(aspi->altr_spi);
> +}
> +
> +#define FME_FEATURE_ID_MAX10_SPI 0xe
> +
> +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> + { FME_ID, FME_FEATURE_ID_MAX10_SPI },
> + { }
> +};
> +
> +static struct dfl_driver dfl_spi_altera_driver = {
> + .drv = {
> + .name = "dfl-spi-altera",
> + },
> + .id_table = dfl_spi_altera_ids,
> + .probe = dfl_spi_altera_probe,
> + .remove = dfl_spi_altera_remove,
> +};
> +
> +module_dfl_driver(dfl_spi_altera_driver);
> +
> +MODULE_DEVICE_TABLE(dfl, dfl_spi_altera_ids);
> +MODULE_DESCRIPTION("DFL spi altera driver");
> +MODULE_AUTHOR("Intel Corporation");
> +MODULE_LICENSE("GPL v2");
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/2] hwmon: intel-m10-bmc-hwmon: add sensor support of Intel D5005 card
2021-04-13 22:58 ` [PATCH v2 2/2] hwmon: intel-m10-bmc-hwmon: add sensor support of Intel D5005 card matthew.gerlach
2021-04-13 23:11 ` Guenter Roeck
@ 2021-04-14 15:36 ` Tom Rix
1 sibling, 0 replies; 9+ messages in thread
From: Tom Rix @ 2021-04-14 15:36 UTC (permalink / raw)
To: matthew.gerlach, hao.wu, mdf, linux-fpga, linux-kernel, yilun.xu,
jdelvare, linux, lee.jones, linux-hwmon, russell.h.weight,
broonie, linux-spi
Cc: Russ Weight
On 4/13/21 3:58 PM, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>
> Like the Intel N3000 card, the Intel D5005 has a MAX10 based
> BMC. This commit adds support for the D5005 sensors that are
> monitored by the MAX10 BMC.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Signed-off-by: Russ Weight <russell.h.weight@linux.intel.com>
> Acked-by: Lee Jones <lee.jones@linaro.org>
lgtm
Reviewed-by: Tom Rix <trix@redhat.com>
> ---
> v2: change variable name from m10bmc_bmc_subdevs to m10bmc_d5005_subdevs
> added Acked-by: Lee Jones
> ---
> drivers/hwmon/intel-m10-bmc-hwmon.c | 122 ++++++++++++++++++++++++++++++++++++
> drivers/mfd/intel-m10-bmc.c | 10 +++
> 2 files changed, 132 insertions(+)
>
> diff --git a/drivers/hwmon/intel-m10-bmc-hwmon.c b/drivers/hwmon/intel-m10-bmc-hwmon.c
> index 17d5e6b..bd7ed2e 100644
> --- a/drivers/hwmon/intel-m10-bmc-hwmon.c
> +++ b/drivers/hwmon/intel-m10-bmc-hwmon.c
> @@ -99,6 +99,50 @@ struct m10bmc_hwmon {
> NULL
> };
>
> +static const struct m10bmc_sdata d5005bmc_temp_tbl[] = {
> + { 0x100, 0x104, 0x108, 0x10c, 0x0, 500, "Board Inlet Air Temperature" },
> + { 0x110, 0x114, 0x118, 0x0, 0x0, 500, "FPGA Core Temperature" },
> + { 0x11c, 0x120, 0x124, 0x128, 0x0, 500, "Board Exhaust Air Temperature" },
> + { 0x12c, 0x130, 0x134, 0x0, 0x0, 500, "FPGA Transceiver Temperature" },
> + { 0x138, 0x13c, 0x140, 0x144, 0x0, 500, "RDIMM0 Temperature" },
> + { 0x148, 0x14c, 0x150, 0x154, 0x0, 500, "RDIMM1 Temperature" },
> + { 0x158, 0x15c, 0x160, 0x164, 0x0, 500, "RDIMM2 Temperature" },
> + { 0x168, 0x16c, 0x170, 0x174, 0x0, 500, "RDIMM3 Temperature" },
> + { 0x178, 0x17c, 0x180, 0x0, 0x0, 500, "QSFP0 Temperature" },
> + { 0x188, 0x18c, 0x190, 0x0, 0x0, 500, "QSFP1 Temperature" },
> + { 0x1a0, 0x1a4, 0x1a8, 0x0, 0x0, 500, "3.3v Temperature" },
> + { 0x1bc, 0x1c0, 0x1c4, 0x0, 0x0, 500, "VCCERAM Temperature" },
> + { 0x1d8, 0x1dc, 0x1e0, 0x0, 0x0, 500, "VCCR Temperature" },
> + { 0x1f4, 0x1f8, 0x1fc, 0x0, 0x0, 500, "VCCT Temperature" },
> + { 0x210, 0x214, 0x218, 0x0, 0x0, 500, "1.8v Temperature" },
> + { 0x22c, 0x230, 0x234, 0x0, 0x0, 500, "12v Backplane Temperature" },
> + { 0x248, 0x24c, 0x250, 0x0, 0x0, 500, "12v AUX Temperature" },
> +};
> +
> +static const struct m10bmc_sdata d5005bmc_in_tbl[] = {
> + { 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QSFP0 Supply Voltage" },
> + { 0x194, 0x0, 0x0, 0x0, 0x0, 1, "QSFP1 Supply Voltage" },
> + { 0x198, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage" },
> + { 0x1ac, 0x1b0, 0x1b4, 0x0, 0x0, 1, "3.3v Voltage" },
> + { 0x1c8, 0x1cc, 0x1d0, 0x0, 0x0, 1, "VCCERAM Voltage" },
> + { 0x1e4, 0x1e8, 0x1ec, 0x0, 0x0, 1, "VCCR Voltage" },
> + { 0x200, 0x204, 0x208, 0x0, 0x0, 1, "VCCT Voltage" },
> + { 0x21c, 0x220, 0x224, 0x0, 0x0, 1, "1.8v Voltage" },
> + { 0x238, 0x0, 0x0, 0x0, 0x23c, 1, "12v Backplane Voltage" },
> + { 0x254, 0x0, 0x0, 0x0, 0x258, 1, "12v AUX Voltage" },
> +};
> +
> +static const struct m10bmc_sdata d5005bmc_curr_tbl[] = {
> + { 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Current" },
> + { 0x1b8, 0x0, 0x0, 0x0, 0x0, 1, "3.3v Current" },
> + { 0x1d4, 0x0, 0x0, 0x0, 0x0, 1, "VCCERAM Current" },
> + { 0x1f0, 0x0, 0x0, 0x0, 0x0, 1, "VCCR Current" },
> + { 0x20c, 0x0, 0x0, 0x0, 0x0, 1, "VCCT Current" },
> + { 0x228, 0x0, 0x0, 0x0, 0x0, 1, "1.8v Current" },
> + { 0x240, 0x244, 0x0, 0x0, 0x0, 1, "12v Backplane Current" },
> + { 0x25c, 0x260, 0x0, 0x0, 0x0, 1, "12v AUX Current" },
> +};
> +
> static const struct m10bmc_hwmon_board_data n3000bmc_hwmon_bdata = {
> .tables = {
> [hwmon_temp] = n3000bmc_temp_tbl,
> @@ -110,6 +154,80 @@ struct m10bmc_hwmon {
> .hinfo = n3000bmc_hinfo,
> };
>
> +static const struct hwmon_channel_info *d5005bmc_hinfo[] = {
> + HWMON_CHANNEL_INFO(temp,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
> + HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
> + HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
> + HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
> + HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
> + HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
> + HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL,
> + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
> + HWMON_T_LABEL),
> + HWMON_CHANNEL_INFO(in,
> + HWMON_I_INPUT | HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
> + HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
> + HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
> + HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
> + HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
> + HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_LABEL,
> + HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_LABEL),
> + HWMON_CHANNEL_INFO(curr,
> + HWMON_C_INPUT | HWMON_C_LABEL,
> + HWMON_C_INPUT | HWMON_C_LABEL,
> + HWMON_C_INPUT | HWMON_C_LABEL,
> + HWMON_C_INPUT | HWMON_C_LABEL,
> + HWMON_C_INPUT | HWMON_C_LABEL,
> + HWMON_C_INPUT | HWMON_C_LABEL,
> + HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_LABEL,
> + HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_LABEL),
> + NULL
> +};
> +
> +static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = {
> + .tables = {
> + [hwmon_temp] = d5005bmc_temp_tbl,
> + [hwmon_in] = d5005bmc_in_tbl,
> + [hwmon_curr] = d5005bmc_curr_tbl,
> + },
> +
> + .hinfo = d5005bmc_hinfo,
> +};
> +
> static umode_t
> m10bmc_hwmon_is_visible(const void *data, enum hwmon_sensor_types type,
> u32 attr, int channel)
> @@ -316,6 +434,10 @@ static int m10bmc_hwmon_probe(struct platform_device *pdev)
> .name = "n3000bmc-hwmon",
> .driver_data = (unsigned long)&n3000bmc_hwmon_bdata,
> },
> + {
> + .name = "d5005bmc-hwmon",
> + .driver_data = (unsigned long)&d5005bmc_hwmon_bdata,
> + },
> { }
> };
>
> diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c
> index 1161933..1a9bfb7 100644
> --- a/drivers/mfd/intel-m10-bmc.c
> +++ b/drivers/mfd/intel-m10-bmc.c
> @@ -15,6 +15,11 @@
>
> enum m10bmc_type {
> M10_N3000,
> + M10_D5005
> +};
> +
> +static struct mfd_cell m10bmc_d5005_subdevs[] = {
> + { .name = "d5005bmc-hwmon" },
> };
>
> static struct mfd_cell m10bmc_pacn3000_subdevs[] = {
> @@ -183,6 +188,10 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
> cells = m10bmc_pacn3000_subdevs;
> n_cell = ARRAY_SIZE(m10bmc_pacn3000_subdevs);
> break;
> + case M10_D5005:
> + cells = m10bmc_d5005_subdevs;
> + n_cell = ARRAY_SIZE(m10bmc_d5005_subdevs);
> + break;
> default:
> return -ENODEV;
> }
> @@ -197,6 +206,7 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
>
> static const struct spi_device_id m10bmc_spi_id[] = {
> { "m10-n3000", M10_N3000 },
> + { "m10-d5005", M10_D5005 },
> { }
> };
> MODULE_DEVICE_TABLE(spi, m10bmc_spi_id);
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] spi: Add DFL bus driver for Altera SPI Master
2021-04-14 14:18 ` Mark Brown
@ 2021-04-14 19:09 ` matthew.gerlach
2021-04-15 11:44 ` Mark Brown
0 siblings, 1 reply; 9+ messages in thread
From: matthew.gerlach @ 2021-04-14 19:09 UTC (permalink / raw)
To: Mark Brown
Cc: hao.wu, trix, mdf, linux-fpga, linux-kernel, yilun.xu, jdelvare,
linux, lee.jones, linux-hwmon, russell.h.weight, linux-spi
On Wed, 14 Apr 2021, Mark Brown wrote:
> On Tue, Apr 13, 2021 at 03:58:34PM -0700, matthew.gerlach@linux.intel.com wrote:
>
>> +++ b/drivers/spi/spi-altera-dfl.c
>> @@ -0,0 +1,222 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * DFL bus driver for Altera SPI Master
>> + *
>
> Please make the entire comment a C++ one so things look more
> intentional.
Ok, I'll change it in the next revision.
>
>> + memset(&pdevinfo, 0, sizeof(pdevinfo));
>> +
>> + pdevinfo.name = "subdev_spi_altera";
>> + pdevinfo.id = PLATFORM_DEVID_AUTO;
>> + pdevinfo.parent = dev;
>> + pdevinfo.data = &pdata;
>> + pdevinfo.size_data = sizeof(pdata);
>> +
>> + return platform_device_register_full(&pdevinfo);
>
> Don't create a platform device here, extend the spi-altera driver to
> register with both DFL and platform buses.
>
Are you suggesting something like the SPI driver for the Designware
controller where there is spi-dw-core.c and bus specific code like
spi-dw-pci.c and spi-dw-mmioc.c?
Thanks for the review.
Matthew
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] spi: Add DFL bus driver for Altera SPI Master
2021-04-14 19:09 ` matthew.gerlach
@ 2021-04-15 11:44 ` Mark Brown
0 siblings, 0 replies; 9+ messages in thread
From: Mark Brown @ 2021-04-15 11:44 UTC (permalink / raw)
To: matthew.gerlach
Cc: hao.wu, trix, mdf, linux-fpga, linux-kernel, yilun.xu, jdelvare,
linux, lee.jones, linux-hwmon, russell.h.weight, linux-spi
[-- Attachment #1: Type: text/plain, Size: 433 bytes --]
On Wed, Apr 14, 2021 at 12:09:50PM -0700, matthew.gerlach@linux.intel.com wrote:
> On Wed, 14 Apr 2021, Mark Brown wrote:
> > Don't create a platform device here, extend the spi-altera driver to
> > register with both DFL and platform buses.
> Are you suggesting something like the SPI driver for the Designware
> controller where there is spi-dw-core.c and bus specific code like
> spi-dw-pci.c and spi-dw-mmioc.c?
Yes, exactly.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-04-15 11:44 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-13 22:58 [PATCH v2 0/2] spi: add BMC support for Intel D5005 card matthew.gerlach
2021-04-13 22:58 ` [PATCH v2 1/2] spi: Add DFL bus driver for Altera SPI Master matthew.gerlach
2021-04-14 14:18 ` Mark Brown
2021-04-14 19:09 ` matthew.gerlach
2021-04-15 11:44 ` Mark Brown
2021-04-14 15:29 ` Tom Rix
2021-04-13 22:58 ` [PATCH v2 2/2] hwmon: intel-m10-bmc-hwmon: add sensor support of Intel D5005 card matthew.gerlach
2021-04-13 23:11 ` Guenter Roeck
2021-04-14 15:36 ` Tom Rix
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