From: Vignesh Raghavendra <vigneshr@ti.com>
To: "Ramuthevar,Vadivel MuruganX"
<vadivel.muruganx.ramuthevar@linux.intel.com>,
<linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>,
<broonie@kernel.org>, <robh+dt@kernel.org>
Cc: marex@denx.de, devicetree@vger.kernel.org,
tien.fong.chee@intel.com, tudor.ambarus@gmail.com,
boris.brezillon@free-electrons.com, richard@nod.at,
qi-ming.wu@intel.com, simon.k.r.goldschmidt@gmail.com,
dinguyen@kernel.org, linux-mtd@lists.infradead.org,
miquel.raynal@bootlin.com, cheol.yong.kim@intel.com,
cyrille.pitchen@atmel.com, computersforpeace@gmail.com,
dwmw2@infradead.org, david.oberhollenzer@sigma-star.at
Subject: Re: [PATCH v12 1/4] dt-bindings: spi: Add schema for Cadence QSPI Controller driver
Date: Fri, 20 Mar 2020 11:35:57 +0530 [thread overview]
Message-ID: <c2ad909e-9042-6ba0-7213-83346c6b9908@ti.com> (raw)
In-Reply-To: <20200310015213.1734-2-vadivel.muruganx.ramuthevar@linux.intel.com>
On 10/03/20 7:22 am, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>
> Add dt-bindings documentation for Cadence-QSPI controller to support
> spi based flash memories.
>
> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> ---
> .../devicetree/bindings/mtd/cadence-quadspi.txt | 67 -----------
> .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 127 +++++++++++++++++++++
> 2 files changed, 127 insertions(+), 67 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> create mode 100644 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>
[...]
> +
> +# subnode's properties
> +patternProperties:
> + "^.*@[0-9a-fA-F]+$":
> + type: object
> + description:
> + flash device uses the subnodes below defined properties.
> +
> + cdns,read-delay:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Delay in 4 microseconds, read capture logic, in clock cycles.
Not its not... See the old binding description please:
-- cdns,read-delay : Delay for read capture logic, in clock cycles
There is no mention of 4us. Range is 0x0 - 0xF
> +
> + cdns,tshsl-ns:
> + description: |
> + Delay in 50 nanoseconds, for the length that the master mode chip select
> + outputs are de-asserted between transactions.
Again see the description in old binding file:
cdns,tshsl-ns : Delay in nanoseconds for the length that the master
mode chip select outputs are de-asserted between
transactions.
Need not be 50ns or its multiple
> +
> + cdns,tsd2d-ns:
> + description: |
> + Delay in 50 nanoseconds, between one chip select being de-activated
> + and the activation of another.
> +
same here
> + cdns,tchsh-ns:
> + description: |
> + Delay in 4 nanoseconds, between last bit of current transaction and
> + deasserting the device chip select (qspi_n_ss_out).
> +
Same here... Need not be 4ns...
> + cdns,tslch-ns:
> + description: |
> + Delay in 4 nanoseconds, between setting qspi_n_ss_out low and
> + first bit transfer.
Same here...
Above four values ( cdns,*-ns) come directly from the flash datasheets.
These values are converted appropriate number of cycles depending upon
the QSPI ref_clk frequency. So, there is no easy way to express the
constraint (or range) in DT schema. I would recommend to just stick with
the description that is there in the old binding file without any
modifications.
Regards
Vignesh
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next prev parent reply other threads:[~2020-03-20 6:05 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-10 1:52 [PATCH v12 0/4] spi: cadence-quadspi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX
[not found] ` <20200310015213.1734-1-vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2020-03-10 1:52 ` [PATCH v12 1/4] dt-bindings: spi: Add schema for Cadence QSPI Controller driver Ramuthevar,Vadivel MuruganX
2020-03-19 18:44 ` Rob Herring
2020-03-20 2:33 ` Ramuthevar, Vadivel MuruganX
2020-03-20 6:05 ` Vignesh Raghavendra [this message]
[not found] ` <c2ad909e-9042-6ba0-7213-83346c6b9908-l0cyMroinI0@public.gmane.org>
2020-03-20 6:19 ` Ramuthevar, Vadivel MuruganX
2020-03-10 1:52 ` [PATCH v12 2/4] mtd: spi-nor: add spi-mem support in cadence-quadspi controller driver Ramuthevar,Vadivel MuruganX
[not found] ` <20200310015213.1734-3-vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2020-03-19 8:09 ` Tudor.Ambarus-UWL1GkI3JZL3oGB3hsPCZA
2020-03-19 9:30 ` Vignesh Raghavendra
2020-03-10 1:52 ` [PATCH v12 3/4] spi: cadence-quadspi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX
2020-03-10 1:52 ` [PATCH v12 4/4] spi: cadence-quadspi: Add qspi support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
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